paging.py « sim « tb - conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

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path: root/tb/sim/paging.py

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cycles = 4096

def final():
    assert_reg(r0, 0x01234567)
    assert_reg(r1, 0x89abcdef)
    assert_reg(r2, 0x89abcde0)
    assert_reg(r3, 0b0101) # Section translation fault, p. 720
    assert_reg(r4, read_reg(r5))