hazards.py « sim « tb - conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

summary refs log tree commit diff

path: root/tb/sim/hazards.py

blob: 8699c47396d579759ac05986c53e92d52b54a975 (plain)

SP = 256

cycles = 1024
mem_dumps = [range(SP - 4, SP)]

def final():
    assert_reg(r0, 59)
    assert_reg(r1, 0)
    assert_reg(sp_svc, SP)
    assert_mem(SP - 4, 3)