1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
|
#ifndef TALLER_AVALON_IMPL_HPP
#define TALLER_AVALON_IMPL_HPP
#include <cassert>
#include <cstdio>
namespace taller::avalon
{
template<class Platform>
inline interconnect<Platform>::interconnect(Platform &plat) noexcept
: plat(plat)
{}
template<class Platform>
void interconnect<Platform>::attach(slave &dev)
{
auto base = dev.base_address();
auto mask = dev.address_mask();
assert((base & mask) == base);
devices.push_back(binding { base, mask, dev });
}
template<class Platform>
bool interconnect<Platform>::tick(bool clk)
{
if(!plat.reset_reset_n) [[unlikely]]
{
active = nullptr;
avl_read = false;
avl_write = false;
avl_address = 0;
avl_writedata = 0;
avl_byteenable = 0;
return true;
}
if(active)
{
assert(avl_address == plat.avl_address);
assert(avl_read == plat.avl_read);
assert(avl_write == plat.avl_write);
assert(avl_writedata == plat.avl_writedata);
assert(avl_byteenable == plat.avl_byteenable);
}
if(!clk)
{
if(!plat.avl_waitrequest)
{
active = nullptr;
}
return true;
} else if(!active)
{
avl_address = plat.avl_address;
avl_read = plat.avl_read;
avl_write = plat.avl_write;
avl_writedata = plat.avl_writedata;
avl_byteenable = plat.avl_byteenable;
assert(!avl_read || !avl_write);
if(!avl_read && !avl_write)
{
return true;
}
for(auto &binding : devices)
{
if((avl_address & binding.mask) == binding.base)
{
active = &binding.dev;
break;
}
}
if(!active)
{
const char *op = avl_read ? "read" : "write";
fprintf(stderr, "[avl] attempt to %s memory hole at 0x%08x\n", op, avl_address);
return false;
}
if(avl_address & active->word_mask())
{
fprintf(stderr, "[avl] unaligned address: 0x%08x\n", avl_address);
return false;
}
}
auto pos = (avl_address & ~active->address_mask()) >> active->word_bits();
if(avl_read)
{
std::uint32_t readdata;
plat.avl_waitrequest = !active->read(pos, readdata);
plat.avl_readdata = readdata;
} else if(avl_write)
{
plat.avl_waitrequest = !active->write(pos, avl_writedata, avl_byteenable);
}
return true;
}
template<class Platform>
std::uint32_t interconnect<Platform>::dump(std::uint32_t addr)
{
std::uint32_t avl_address = addr << 2;
for(auto &binding : devices)
{
if((avl_address & binding.mask) == binding.base)
{
auto &dev = binding.dev;
auto pos = (avl_address & ~dev.address_mask()) >> 2;
std::uint32_t readdata;
while(!dev.read(pos, readdata))
{
continue;
}
return readdata;
}
}
fprintf(stderr, "[avl] attempt to dump memory hole at 0x%08x\n", addr);
assert(false);
}
}
#endif
|
