rtl/core/cp15/domain.sv


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

`include "core/uarch.sv"

module core_cp15_domain
(
	input  logic     clk,
	                 rst_n,

	input  logic     load,
	                 transfer,
	input  word      write,

	output word      read,
	                 mmu_dac /*verilator public*/
);

	assign read = mmu_dac;

	always @(posedge clk or negedge rst_n)
		if(!rst_n)
			mmu_dac <= 0;
		else if(transfer && !load)
			mmu_dac <= write;

endmodule