blob: e3644c4d3f5b8948ac598f562a323dca41837df6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
`include "core/uarch.sv"
module core_control_issue
(
input logic clk,
input insn_decode dec,
input ptr insn_pc,
input ctrl_cycle next_cycle,
input logic next_bubble,
`ifdef VERILATOR
input word insn,
`endif
output logic issue,
undefined,
output ptr pc,
pc_visible,
next_pc_visible
);
assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
assign next_pc_visible = insn_pc + 2;
always_ff @(posedge clk)
if(next_cycle == ISSUE) begin
undefined <= dec.ctrl.undefined;
`ifdef VERILATOR
if(dec.ctrl.undefined)
$display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn);
`endif
pc <= insn_pc;
pc_visible <= next_pc_visible;
end
initial begin
pc = 0;
pc_visible = 2;
undefined = 0;
end
endmodule
|
