1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
|
`include "core/uarch.sv"
module core_control_exception
(
input logic clk,
rst_n,
input ctrl_cycle next_cycle,
input logic high_vectors,
undefined,
mem_fault,
output logic exception,
exception_offset_pc,
output psr_mode exception_mode,
output word exception_vector
);
logic[2:0] vector_offset;
//TODO: irq, fiq, prefetch abort, swi
assign exception = undefined || mem_fault;
assign exception_vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
vector_offset <= 0;
exception_mode <= 0;
exception_offset_pc <= 0;
end else if(mem_fault) begin
vector_offset <= 3'b100;
exception_mode <= `MODE_ABT;
end else if(undefined) begin
vector_offset <= 3'b001;
exception_mode <= `MODE_UND;
end
if(next_cycle.escalate)
exception_offset_pc <= !mem_fault;
end
endmodule
|
