# TCL File Generated by Component Editor 20.1 # Sat Sep 30 05:54:51 GMT 2023 # DO NOT MODIFY # # smp "SMP controller" v1.0 # 2023.09.30.05:54:51 # # # # request TCL package from ACDS 16.1 # package require -exact qsys 16.1 # # module smp # set_module_property DESCRIPTION "" set_module_property NAME smp set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property AUTHOR "" set_module_property DISPLAY_NAME "SMP controller" set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false set_module_property REPORT_HIERARCHY false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL smp_ctrl set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file smp_ctrl.sv SYSTEM_VERILOG PATH rtl/smp/smp_ctrl.sv TOP_LEVEL_FILE add_fileset_file pe.sv SYSTEM_VERILOG PATH rtl/smp/pe.sv # # parameters # # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point avl # add_interface avl avalon end set_interface_property avl addressUnits WORDS set_interface_property avl associatedClock clock set_interface_property avl associatedReset reset_sink set_interface_property avl bitsPerSymbol 8 set_interface_property avl burstOnBurstBoundariesOnly false set_interface_property avl burstcountUnits WORDS set_interface_property avl explicitAddressSpan 0 set_interface_property avl holdTime 0 set_interface_property avl linewrapBursts false set_interface_property avl maximumPendingReadTransactions 0 set_interface_property avl maximumPendingWriteTransactions 0 set_interface_property avl readLatency 0 set_interface_property avl readWaitTime 1 set_interface_property avl setupTime 0 set_interface_property avl timingUnits Cycles set_interface_property avl writeWaitTime 0 set_interface_property avl ENABLED true set_interface_property avl EXPORT_OF "" set_interface_property avl PORT_NAME_MAP "" set_interface_property avl CMSIS_SVD_VARIABLES "" set_interface_property avl SVD_ADDRESS_GROUP "" add_interface_port avl avl_read read Input 1 add_interface_port avl avl_write write Input 1 add_interface_port avl avl_writedata writedata Input 32 add_interface_port avl avl_readdata readdata Output 32 set_interface_assignment avl embeddedsw.configuration.isFlash 0 set_interface_assignment avl embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment avl embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment avl embeddedsw.configuration.isPrintableDevice 0 # # connection point reset_sink # add_interface reset_sink reset end set_interface_property reset_sink associatedClock clock set_interface_property reset_sink synchronousEdges DEASSERT set_interface_property reset_sink ENABLED true set_interface_property reset_sink EXPORT_OF "" set_interface_property reset_sink PORT_NAME_MAP "" set_interface_property reset_sink CMSIS_SVD_VARIABLES "" set_interface_property reset_sink SVD_ADDRESS_GROUP "" add_interface_port reset_sink rst_n reset_n Input 1 # # connection point cpu_0 # add_interface cpu_0 conduit end set_interface_property cpu_0 associatedClock clock set_interface_property cpu_0 associatedReset reset_sink set_interface_property cpu_0 ENABLED true set_interface_property cpu_0 EXPORT_OF "" set_interface_property cpu_0 PORT_NAME_MAP "" set_interface_property cpu_0 CMSIS_SVD_VARIABLES "" set_interface_property cpu_0 SVD_ADDRESS_GROUP "" add_interface_port cpu_0 halt_0 halt Output 1 add_interface_port cpu_0 step_0 step Output 1 add_interface_port cpu_0 cpu_alive_0 cpu_alive Input 1 add_interface_port cpu_0 cpu_halted_0 cpu_halted Input 1 add_interface_port cpu_0 breakpoint_0 breakpoint Input 1 # # connection point cpu_1 # add_interface cpu_1 conduit end set_interface_property cpu_1 associatedClock clock set_interface_property cpu_1 associatedReset reset_sink set_interface_property cpu_1 ENABLED true set_interface_property cpu_1 EXPORT_OF "" set_interface_property cpu_1 PORT_NAME_MAP "" set_interface_property cpu_1 CMSIS_SVD_VARIABLES "" set_interface_property cpu_1 SVD_ADDRESS_GROUP "" add_interface_port cpu_1 breakpoint_1 breakpoint Input 1 add_interface_port cpu_1 cpu_alive_1 cpu_alive Input 1 add_interface_port cpu_1 cpu_halted_1 cpu_halted Input 1 add_interface_port cpu_1 halt_1 halt Output 1 add_interface_port cpu_1 step_1 step Output 1 # # connection point cpu_2 # add_interface cpu_2 conduit end set_interface_property cpu_2 associatedClock clock set_interface_property cpu_2 associatedReset reset_sink set_interface_property cpu_2 ENABLED true set_interface_property cpu_2 EXPORT_OF "" set_interface_property cpu_2 PORT_NAME_MAP "" set_interface_property cpu_2 CMSIS_SVD_VARIABLES "" set_interface_property cpu_2 SVD_ADDRESS_GROUP "" add_interface_port cpu_2 breakpoint_2 breakpoint Input 1 add_interface_port cpu_2 cpu_alive_2 cpu_alive Input 1 add_interface_port cpu_2 cpu_halted_2 cpu_halted Input 1 add_interface_port cpu_2 halt_2 halt Output 1 add_interface_port cpu_2 step_2 step Output 1 # # connection point cpu_3 # add_interface cpu_3 conduit end set_interface_property cpu_3 associatedClock clock set_interface_property cpu_3 associatedReset reset_sink set_interface_property cpu_3 ENABLED true set_interface_property cpu_3 EXPORT_OF "" set_interface_property cpu_3 PORT_NAME_MAP "" set_interface_property cpu_3 CMSIS_SVD_VARIABLES "" set_interface_property cpu_3 SVD_ADDRESS_GROUP "" add_interface_port cpu_3 breakpoint_3 breakpoint Input 1 add_interface_port cpu_3 cpu_alive_3 cpu_alive Input 1 add_interface_port cpu_3 cpu_halted_3 cpu_halted Input 1 add_interface_port cpu_3 halt_3 halt Output 1 add_interface_port cpu_3 step_3 step Output 1