//IP Functional Simulation Model //VERSION_BEGIN 20.1 cbx_mgl 2020:11:11:17:50:46:SJ cbx_simgen 2020:11:11:17:03:37:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 2020 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions // and other software and tools, and any partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License // Subscription Agreement, the Intel Quartus Prime License Agreement, // the Intel FPGA IP License Agreement, or other applicable license // agreement, including, without limitation, that your use is for // the sole purpose of programming logic devices manufactured by // Intel and sold by Intel or its authorized distributors. Please // refer to the applicable agreement for further details, at // https://fpgasoftware.intel.com/eula. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Intel disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 87 mux21 11 oper_add 5 oper_mult 1 oper_mux 17 `timescale 1 ps / 1 ps module ip_fp_mul ( a, areset, b, clk, en, q) /* synthesis synthesis_clearbox=1 */; input [15:0] a; input areset; input [15:0] b; input clk; input [0:0] en; output [15:0] q; reg n0ii; reg n0il; reg n0iO; reg n0li; reg n0ll; reg n0Oi; reg n0Ol; reg n0OO; reg n1i; reg n1O; reg ni00i; reg ni00l; reg ni00O; reg ni0i; reg ni0ii; reg ni0il; reg ni0iO; reg ni0l; reg ni0li; reg ni0ll; reg ni0lO; reg ni0O; reg ni0Oi; reg ni0Ol; reg ni0OO; reg ni1i; reg ni1l; reg ni1O; reg nii0i; reg nii0l; reg nii0O; reg nii1i; reg nii1l; reg nii1O; reg niii; reg niiii; reg niiil; reg niiiO; reg niil; reg niili; reg niill; reg niilO; reg niiO; reg niiOi; reg niiOl; reg niiOO; reg nil0i; reg nil0l; reg nil0O; reg nil1i; reg nil1l; reg nil1O; reg nili; reg nilii; reg nilil; reg niliO; reg nill; reg nilli; reg nilll; reg nillO; reg nilO; reg nilOi; reg nilOl; reg nilOO; reg niO0i; reg niO1i; reg niO1l; reg niO1O; reg niOi; reg niOl; reg niOO; reg nl0i; reg nl0l; reg nl0O; reg nl1i; reg nl1l; reg nl1O; reg nlii; reg nlil; reg nliO; reg nlli; reg nlll; reg nllO; reg nlOi; reg nlOl; reg nlOlO; reg nlOO; wire wire_n1l_ENA; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01O_dataout; wire wire_n1li_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1Oi_dataout; wire wire_n1Ol_dataout; wire wire_n1OO_dataout; wire [9:0] wire_n00O_o; wire [5:0] wire_n0lO_o; wire [11:0] wire_n1il_o; wire [20:0] wire_n1iO_o; wire [11:0] wire_nlOll_o; wire [21:0] wire_n0i_o; wire wire_nll0i_o; wire wire_nll0l_o; wire wire_nll0O_o; wire wire_nll1l_o; wire wire_nll1O_o; wire wire_nllii_o; wire wire_nllil_o; wire wire_nlliO_o; wire wire_nllli_o; wire wire_nllll_o; wire wire_nlllO_o; wire wire_nllOi_o; wire wire_nllOl_o; wire wire_nllOO_o; wire wire_nlO1i_o; wire wire_nlO1l_o; wire wire_nlO1O_o; wire ni01i; wire ni10i; wire ni10l; wire ni10O; wire ni11l; wire ni11O; wire ni1ii; wire ni1il; wire ni1iO; wire ni1li; wire ni1ll; wire ni1lO; wire ni1Oi; wire ni1Ol; wire ni1OO; initial begin n0ii = 0; n0il = 0; n0iO = 0; n0li = 0; n0ll = 0; n0Oi = 0; n0Ol = 0; n0OO = 0; n1i = 0; n1O = 0; ni00i = 0; ni00l = 0; ni00O = 0; ni0i = 0; ni0ii = 0; ni0il = 0; ni0iO = 0; ni0l = 0; ni0li = 0; ni0ll = 0; ni0lO = 0; ni0O = 0; ni0Oi = 0; ni0Ol = 0; ni0OO = 0; ni1i = 0; ni1l = 0; ni1O = 0; nii0i = 0; nii0l = 0; nii0O = 0; nii1i = 0; nii1l = 0; nii1O = 0; niii = 0; niiii = 0; niiil = 0; niiiO = 0; niil = 0; niili = 0; niill = 0; niilO = 0; niiO = 0; niiOi = 0; niiOl = 0; niiOO = 0; nil0i = 0; nil0l = 0; nil0O = 0; nil1i = 0; nil1l = 0; nil1O = 0; nili = 0; nilii = 0; nilil = 0; niliO = 0; nill = 0; nilli = 0; nilll = 0; nillO = 0; nilO = 0; nilOi = 0; nilOl = 0; nilOO = 0; niO0i = 0; niO1i = 0; niO1l = 0; niO1O = 0; niOi = 0; niOl = 0; niOO = 0; nl0i = 0; nl0l = 0; nl0O = 0; nl1i = 0; nl1l = 0; nl1O = 0; nlii = 0; nlil = 0; nliO = 0; nlli = 0; nlll = 0; nllO = 0; nlOi = 0; nlOl = 0; nlOlO = 0; nlOO = 0; end always @ ( posedge clk or posedge areset) begin if (areset == 1'b1) begin n0ii <= 0; n0il <= 0; n0iO <= 0; n0li <= 0; n0ll <= 0; n0Oi <= 0; n0Ol <= 0; n0OO <= 0; n1i <= 0; n1O <= 0; ni00i <= 0; ni00l <= 0; ni00O <= 0; ni0i <= 0; ni0ii <= 0; ni0il <= 0; ni0iO <= 0; ni0l <= 0; ni0li <= 0; ni0ll <= 0; ni0lO <= 0; ni0O <= 0; ni0Oi <= 0; ni0Ol <= 0; ni0OO <= 0; ni1i <= 0; ni1l <= 0; ni1O <= 0; nii0i <= 0; nii0l <= 0; nii0O <= 0; nii1i <= 0; nii1l <= 0; nii1O <= 0; niii <= 0; niiii <= 0; niiil <= 0; niiiO <= 0; niil <= 0; niili <= 0; niill <= 0; niilO <= 0; niiO <= 0; niiOi <= 0; niiOl <= 0; niiOO <= 0; nil0i <= 0; nil0l <= 0; nil0O <= 0; nil1i <= 0; nil1l <= 0; nil1O <= 0; nili <= 0; nilii <= 0; nilil <= 0; niliO <= 0; nill <= 0; nilli <= 0; nilll <= 0; nillO <= 0; nilO <= 0; nilOi <= 0; nilOl <= 0; nilOO <= 0; niO0i <= 0; niO1i <= 0; niO1l <= 0; niO1O <= 0; niOi <= 0; niOl <= 0; niOO <= 0; nl0i <= 0; nl0l <= 0; nl0O <= 0; nl1i <= 0; nl1l <= 0; nl1O <= 0; nlii <= 0; nlil <= 0; nliO <= 0; nlli <= 0; nlll <= 0; nllO <= 0; nlOi <= 0; nlOl <= 0; nlOlO <= 0; nlOO <= 0; end else if (wire_n1l_ENA == 1'b1) begin n0ii <= wire_n0lO_o[1]; n0il <= wire_n0lO_o[2]; n0iO <= wire_n0lO_o[3]; n0li <= wire_n0lO_o[4]; n0ll <= wire_n0lO_o[5]; n0Oi <= wire_n0i_o[9]; n0Ol <= wire_n0i_o[10]; n0OO <= wire_n0i_o[11]; n1i <= a[9]; n1O <= ni1Oi; ni00i <= ni1ii; ni00l <= ni00O; ni00O <= ni00i; ni0i <= wire_n0i_o[15]; ni0ii <= a[10]; ni0il <= a[11]; ni0iO <= a[12]; ni0l <= wire_n0i_o[16]; ni0li <= a[13]; ni0ll <= a[14]; ni0lO <= ni10O; ni0O <= wire_n0i_o[17]; ni0Oi <= ni0lO; ni0Ol <= b[10]; ni0OO <= b[11]; ni1i <= wire_n0i_o[12]; ni1l <= wire_n0i_o[13]; ni1O <= wire_n0i_o[14]; nii0i <= ni10l; nii0l <= nii0i; nii0O <= ni10i; nii1i <= b[12]; nii1l <= b[13]; nii1O <= b[14]; niii <= wire_n0i_o[18]; niiii <= niiil; niiil <= nii0O; niiiO <= ni11O; niil <= wire_n0i_o[19]; niili <= niiiO; niill <= ni11l; niilO <= niill; niiO <= wire_n0i_o[20]; niiOi <= (a[15] ^ b[15]); niiOl <= niiOO; niiOO <= niiOi; nil0i <= wire_n1iO_o[14]; nil0l <= wire_n1iO_o[15]; nil0O <= wire_n1iO_o[16]; nil1i <= wire_n1iO_o[11]; nil1l <= wire_n1iO_o[12]; nil1O <= wire_n1iO_o[13]; nili <= wire_n0i_o[21]; nilii <= wire_n1iO_o[17]; nilil <= wire_n1iO_o[18]; niliO <= wire_n1iO_o[19]; nill <= b[0]; nilli <= wire_n1iO_o[1]; nilll <= wire_n1iO_o[2]; nillO <= wire_n1iO_o[3]; nilO <= b[1]; nilOi <= wire_n1iO_o[4]; nilOl <= wire_n1iO_o[5]; nilOO <= wire_n1iO_o[6]; niO0i <= wire_n1iO_o[10]; niO1i <= wire_n1iO_o[7]; niO1l <= wire_n1iO_o[8]; niO1O <= wire_n1iO_o[9]; niOi <= b[2]; niOl <= b[3]; niOO <= b[4]; nl0i <= b[8]; nl0l <= b[9]; nl0O <= ni1Oi; nl1i <= b[5]; nl1l <= b[6]; nl1O <= b[7]; nlii <= a[0]; nlil <= a[1]; nliO <= a[2]; nlli <= a[3]; nlll <= a[4]; nllO <= a[5]; nlOi <= a[6]; nlOl <= a[7]; nlOlO <= wire_n0lO_o[0]; nlOO <= a[8]; end end assign wire_n1l_ENA = en[0]; assign wire_n00i_dataout = ((~ nili) === 1'b1) ? niii : niil; assign wire_n00l_dataout = ((~ nili) === 1'b1) ? niil : niiO; assign wire_n01i_dataout = ((~ nili) === 1'b1) ? ni0i : ni0l; assign wire_n01l_dataout = ((~ nili) === 1'b1) ? ni0l : ni0O; assign wire_n01O_dataout = ((~ nili) === 1'b1) ? ni0O : niii; assign wire_n1li_dataout = ((~ nili) === 1'b1) ? n0Oi : n0Ol; assign wire_n1ll_dataout = ((~ nili) === 1'b1) ? n0Ol : n0OO; assign wire_n1lO_dataout = ((~ nili) === 1'b1) ? n0OO : ni1i; assign wire_n1Oi_dataout = ((~ nili) === 1'b1) ? ni1i : ni1l; assign wire_n1Ol_dataout = ((~ nili) === 1'b1) ? ni1l : ni1O; assign wire_n1OO_dataout = ((~ nili) === 1'b1) ? ni1O : ni0i; oper_add n00O ( .a({{3{1'b0}}, n0ll, n0li, n0iO, n0il, n0ii, nlOlO, 1'b1}), .b({{5{1'b1}}, {4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n00O_o)); defparam n00O.sgate_representation = 0, n00O.width_a = 10, n00O.width_b = 10, n00O.width_o = 10; oper_add n0lO ( .a({1'b0, ni0ll, ni0li, ni0iO, ni0il, ni0ii}), .b({1'b0, nii1O, nii1l, nii1i, ni0OO, ni0Ol}), .cin(1'b0), .cout(), .o(wire_n0lO_o)); defparam n0lO.sgate_representation = 0, n0lO.width_a = 6, n0lO.width_b = 6, n0lO.width_o = 6; oper_add n1il ( .a({{3{niliO}}, nilil, nilii, nil0O, nil0l, nil0i, nil1O, nil1l, nil1i, 1'b1}), .b({{6{1'b1}}, {5{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1il_o)); defparam n1il.sgate_representation = 0, n1il.width_a = 12, n1il.width_b = 12, n1il.width_o = 12; oper_add n1iO ( .a({{2{wire_n00O_o[8]}}, wire_n00O_o[8:1], wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout}), .b({{9{1'b0}}, nili, {10{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1iO_o)); defparam n1iO.sgate_representation = 0, n1iO.width_a = 21, n1iO.width_b = 21, n1iO.width_o = 21; oper_add nlOll ( .a({{3{(~ niliO)}}, (~ nilil), (~ nilii), (~ nil0O), (~ nil0l), (~ nil0i), (~ nil1O), (~ nil1l), (~ nil1i), 1'b1}), .b({{11{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlOll_o)); defparam nlOll.sgate_representation = 0, nlOll.width_a = 12, nlOll.width_b = 12, nlOll.width_o = 12; oper_mult n0i ( .a({n1O, n1i, nlOO, nlOl, nlOi, nllO, nlll, nlli, nliO, nlil, nlii}), .b({nl0O, nl0l, nl0i, nl1O, nl1l, nl1i, niOO, niOl, niOi, nilO, nill}), .o(wire_n0i_o)); defparam n0i.sgate_representation = 0, n0i.width_a = 11, n0i.width_b = 11, n0i.width_o = 22; oper_mux nll0i ( .data({{2{1'b0}}, nillO, 1'b0}), .o(wire_nll0i_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nll0i.width_data = 4, nll0i.width_sel = 2; oper_mux nll0l ( .data({{2{1'b0}}, nilOi, 1'b0}), .o(wire_nll0l_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nll0l.width_data = 4, nll0l.width_sel = 2; oper_mux nll0O ( .data({{2{1'b0}}, nilOl, 1'b0}), .o(wire_nll0O_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nll0O.width_data = 4, nll0O.width_sel = 2; oper_mux nll1l ( .data({1'b1, 1'b0, nilli, 1'b0}), .o(wire_nll1l_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nll1l.width_data = 4, nll1l.width_sel = 2; oper_mux nll1O ( .data({{2{1'b0}}, nilll, 1'b0}), .o(wire_nll1O_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nll1O.width_data = 4, nll1O.width_sel = 2; oper_mux nllii ( .data({{2{1'b0}}, nilOO, 1'b0}), .o(wire_nllii_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nllii.width_data = 4, nllii.width_sel = 2; oper_mux nllil ( .data({{2{1'b0}}, niO1i, 1'b0}), .o(wire_nllil_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nllil.width_data = 4, nllil.width_sel = 2; oper_mux nlliO ( .data({{2{1'b0}}, niO1l, 1'b0}), .o(wire_nlliO_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nlliO.width_data = 4, nlliO.width_sel = 2; oper_mux nllli ( .data({{2{1'b0}}, niO1O, 1'b0}), .o(wire_nllli_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nllli.width_data = 4, nllli.width_sel = 2; oper_mux nllll ( .data({{2{1'b0}}, niO0i, 1'b0}), .o(wire_nllll_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nllll.width_data = 4, nllll.width_sel = 2; oper_mux nlllO ( .data({{2{1'b1}}, nil1i, 1'b0}), .o(wire_nlllO_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nlllO.width_data = 4, nlllO.width_sel = 2; oper_mux nllOi ( .data({{2{1'b1}}, nil1l, 1'b0}), .o(wire_nllOi_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nllOi.width_data = 4, nllOi.width_sel = 2; oper_mux nllOl ( .data({{2{1'b1}}, nil1O, 1'b0}), .o(wire_nllOl_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nllOl.width_data = 4, nllOl.width_sel = 2; oper_mux nllOO ( .data({{2{1'b1}}, nil0i, 1'b0}), .o(wire_nllOO_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nllOO.width_data = 4, nllOO.width_sel = 2; oper_mux nlO1i ( .data({{2{1'b1}}, nil0l, 1'b0}), .o(wire_nlO1i_o), .sel({wire_nlO1O_o, wire_nlO1l_o})); defparam nlO1i.width_data = 4, nlO1i.width_sel = 2; oper_mux nlO1l ( .data({{3{1'b0}}, 1'b1}), .o(wire_nlO1l_o), .sel({ni1iO, ni1il})); defparam nlO1l.width_data = 4, nlO1l.width_sel = 2; oper_mux nlO1O ( .data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}}), .o(wire_nlO1O_o), .sel({ni1Ol, ni1iO, ni1il})); defparam nlO1O.width_data = 8, nlO1O.width_sel = 3; assign ni01i = (ni00l & ni0Oi), ni10i = ((((((((((~ b[0]) & (~ b[1])) & (~ b[2])) & (~ b[3])) & (~ b[4])) & (~ b[5])) & (~ b[6])) & (~ b[7])) & (~ b[8])) & (~ b[9])), ni10l = (((((~ nii1O) & (~ nii1l)) & (~ nii1i)) & (~ ni0OO)) & (~ ni0Ol)), ni10O = ((((ni0ll & ni0li) & ni0iO) & ni0il) & ni0ii), ni11l = (((((~ ni0ll) & (~ ni0li)) & (~ ni0iO)) & (~ ni0il)) & (~ ni0ii)), ni11O = ((((nii1O & nii1l) & nii1i) & ni0OO) & ni0Ol), ni1ii = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])), ni1il = ((ni1li & (~ wire_nlOll_o[11])) | ((ni1ll & nii0l) | ((ni1lO & niilO) | (nii0l & niilO)))), ni1iO = (((~ wire_n1il_o[11]) & ni1li) | ((ni01i & ni1lO) | ((ni1OO & ni1ll) | (ni01i & ni1OO)))), ni1li = (ni1lO & ni1ll), ni1ll = ((~ ni0Oi) & (~ niilO)), ni1lO = ((~ nii0l) & (~ niili)), ni1Oi = 1'b1, ni1Ol = (((ni01i & nii0l) | (ni1OO & niilO)) | (((~ niiii) & niili) | ((~ ni00l) & ni0Oi))), ni1OO = (niiii & niili), q = {((~ ni1Ol) & niiOl), wire_nlO1i_o, wire_nllOO_o, wire_nllOl_o, wire_nllOi_o, wire_nlllO_o, wire_nllll_o, wire_nllli_o, wire_nlliO_o, wire_nllil_o, wire_nllii_o, wire_nll0O_o, wire_nll0l_o, wire_nll0i_o, wire_nll1O_o, wire_nll1l_o}; endmodule //ip_fp_mul //synopsys translate_on //VALID FILE