component dsp_mul is
		port (
			result  : out std_logic_vector(63 downto 0);                    -- result
			dataa_0 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- dataa_0
			datab_0 : in  std_logic_vector(31 downto 0) := (others => 'X'); -- datab_0
			signa   : in  std_logic                     := 'X';             -- signa
			signb   : in  std_logic                     := 'X';             -- signb
			clock0  : in  std_logic                     := 'X';             -- clock0
			ena0    : in  std_logic                     := 'X';             -- ena0
			aclr0   : in  std_logic                     := 'X';             -- aclr0
			chainin : in  std_logic_vector(63 downto 0) := (others => 'X')  -- chainin
		);
	end component dsp_mul;