# TCL File Generated by Component Editor 20.1
# Mon Oct 02 22:54:00 GMT 2023
# DO NOT MODIFY


# 
# core "ARM810 CPU" v1.0
#  2023.10.02.22:54:00
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module core
# 
set_module_property DESCRIPTION ""
set_module_property NAME core
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "ARM810 CPU"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL core
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file arm810.sv SYSTEM_VERILOG PATH rtl/core/arm810.sv
add_fileset_file bus_master.sv SYSTEM_VERILOG PATH rtl/core/bus_master.sv
add_fileset_file core.sv SYSTEM_VERILOG PATH rtl/core/core.sv TOP_LEVEL_FILE
add_fileset_file core_alu.sv SYSTEM_VERILOG PATH rtl/core/core_alu.sv
add_fileset_file core_alu_add.sv SYSTEM_VERILOG PATH rtl/core/core_alu_add.sv
add_fileset_file core_alu_and.sv SYSTEM_VERILOG PATH rtl/core/core_alu_and.sv
add_fileset_file core_alu_orr.sv SYSTEM_VERILOG PATH rtl/core/core_alu_orr.sv
add_fileset_file core_alu_xor.sv SYSTEM_VERILOG PATH rtl/core/core_alu_xor.sv
add_fileset_file core_control.sv SYSTEM_VERILOG PATH rtl/core/core_control.sv
add_fileset_file core_control_branch.sv SYSTEM_VERILOG PATH rtl/core/core_control_branch.sv
add_fileset_file core_control_coproc.sv SYSTEM_VERILOG PATH rtl/core/core_control_coproc.sv
add_fileset_file core_control_cycles.sv SYSTEM_VERILOG PATH rtl/core/core_control_cycles.sv
add_fileset_file core_control_data.sv SYSTEM_VERILOG PATH rtl/core/core_control_data.sv
add_fileset_file core_control_debug.sv SYSTEM_VERILOG PATH rtl/core/core_control_debug.sv
add_fileset_file core_control_exception.sv SYSTEM_VERILOG PATH rtl/core/core_control_exception.sv
add_fileset_file core_control_issue.sv SYSTEM_VERILOG PATH rtl/core/core_control_issue.sv
add_fileset_file core_control_ldst.sv SYSTEM_VERILOG PATH rtl/core/core_control_ldst.sv
add_fileset_file core_control_ldst_pop.sv SYSTEM_VERILOG PATH rtl/core/core_control_ldst_pop.sv
add_fileset_file core_control_ldst_sizes.sv SYSTEM_VERILOG PATH rtl/core/core_control_ldst_sizes.sv
add_fileset_file core_control_mul.sv SYSTEM_VERILOG PATH rtl/core/core_control_mul.sv
add_fileset_file core_control_psr.sv SYSTEM_VERILOG PATH rtl/core/core_control_psr.sv
add_fileset_file core_control_select.sv SYSTEM_VERILOG PATH rtl/core/core_control_select.sv
add_fileset_file core_control_stall.sv SYSTEM_VERILOG PATH rtl/core/core_control_stall.sv
add_fileset_file core_control_writeback.sv SYSTEM_VERILOG PATH rtl/core/core_control_writeback.sv
add_fileset_file core_cp15.sv SYSTEM_VERILOG PATH rtl/core/core_cp15.sv
add_fileset_file core_cp15_cache.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cache.sv
add_fileset_file core_cp15_cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cache_lockdown.sv
add_fileset_file core_cp15_cpuid.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cpuid.sv
add_fileset_file core_cp15_cyclecnt.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cyclecnt.sv
add_fileset_file core_cp15_domain.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_domain.sv
add_fileset_file core_cp15_far.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_far.sv
add_fileset_file core_cp15_fsr.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_fsr.sv
add_fileset_file core_cp15_syscfg.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_syscfg.sv
add_fileset_file core_cp15_tlb.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_tlb.sv
add_fileset_file core_cp15_tlb_lockdown.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_tlb_lockdown.sv
add_fileset_file core_cp15_ttbr.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_ttbr.sv
add_fileset_file core_decode.sv SYSTEM_VERILOG PATH rtl/core/core_decode.sv
add_fileset_file core_decode_branch.sv SYSTEM_VERILOG PATH rtl/core/core_decode_branch.sv
add_fileset_file core_decode_coproc.sv SYSTEM_VERILOG PATH rtl/core/core_decode_coproc.sv
add_fileset_file core_decode_data.sv SYSTEM_VERILOG PATH rtl/core/core_decode_data.sv
add_fileset_file core_decode_ldst_addr.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_addr.sv
add_fileset_file core_decode_ldst_exclusive.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_exclusive.sv
add_fileset_file core_decode_ldst_misc.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_misc.sv
add_fileset_file core_decode_ldst_multiple.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_multiple.sv
add_fileset_file core_decode_ldst_single.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_single.sv
add_fileset_file core_decode_mrs.sv SYSTEM_VERILOG PATH rtl/core/core_decode_mrs.sv
add_fileset_file core_decode_msr.sv SYSTEM_VERILOG PATH rtl/core/core_decode_msr.sv
add_fileset_file core_decode_mul.sv SYSTEM_VERILOG PATH rtl/core/core_decode_mul.sv
add_fileset_file core_decode_mux.sv SYSTEM_VERILOG PATH rtl/core/core_decode_mux.sv
add_fileset_file core_decode_snd.sv SYSTEM_VERILOG PATH rtl/core/core_decode_snd.sv
add_fileset_file core_fetch.sv SYSTEM_VERILOG PATH rtl/core/core_fetch.sv
add_fileset_file core_mmu.sv SYSTEM_VERILOG PATH rtl/core/core_mmu.sv
add_fileset_file core_mmu_arbiter.sv SYSTEM_VERILOG PATH rtl/core/core_mmu_arbiter.sv
add_fileset_file core_mmu_fault.sv SYSTEM_VERILOG PATH rtl/core/core_mmu_fault.sv
add_fileset_file core_mmu_pagewalk.sv SYSTEM_VERILOG PATH rtl/core/core_mmu_pagewalk.sv
add_fileset_file core_mul.sv SYSTEM_VERILOG PATH rtl/core/core_mul.sv
add_fileset_file core_porch.sv SYSTEM_VERILOG PATH rtl/core/core_porch.sv
add_fileset_file core_porch_conds.sv SYSTEM_VERILOG PATH rtl/core/core_porch_conds.sv
add_fileset_file core_prefetch.sv SYSTEM_VERILOG PATH rtl/core/core_prefetch.sv
add_fileset_file core_psr.sv SYSTEM_VERILOG PATH rtl/core/core_psr.sv
add_fileset_file core_reg_file.sv SYSTEM_VERILOG PATH rtl/core/core_reg_file.sv
add_fileset_file core_reg_map.sv SYSTEM_VERILOG PATH rtl/core/core_reg_map.sv
add_fileset_file core_regs.sv SYSTEM_VERILOG PATH rtl/core/core_regs.sv
add_fileset_file core_shifter.sv SYSTEM_VERILOG PATH rtl/core/core_shifter.sv
add_fileset_file cp15_map.sv SYSTEM_VERILOG PATH rtl/core/cp15_map.sv
add_fileset_file isa.sv SYSTEM_VERILOG PATH rtl/core/isa.sv
add_fileset_file mmu_format.sv SYSTEM_VERILOG PATH rtl/core/mmu_format.sv
add_fileset_file uarch.sv SYSTEM_VERILOG PATH rtl/core/uarch.sv


# 
# parameters
# 
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID ALLOWED_RANGES 0:3
set_parameter_property ID AFFECTS_GENERATION false
set_parameter_property ID HDL_PARAMETER true


# 
# display items
# 


# 
# connection point clock_sink
# 
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""

add_interface_port clock_sink clk clk Input 1


# 
# connection point master
# 
add_interface master avalon start
set_interface_property master addressUnits SYMBOLS
set_interface_property master associatedClock clock_sink
set_interface_property master associatedReset reset_sink
set_interface_property master bitsPerSymbol 8
set_interface_property master burstOnBurstBoundariesOnly false
set_interface_property master burstcountUnits WORDS
set_interface_property master doStreamReads false
set_interface_property master doStreamWrites false
set_interface_property master holdTime 0
set_interface_property master linewrapBursts false
set_interface_property master maximumPendingReadTransactions 0
set_interface_property master maximumPendingWriteTransactions 0
set_interface_property master readLatency 0
set_interface_property master readWaitTime 1
set_interface_property master setupTime 0
set_interface_property master timingUnits Cycles
set_interface_property master writeWaitTime 0
set_interface_property master ENABLED true
set_interface_property master EXPORT_OF ""
set_interface_property master PORT_NAME_MAP ""
set_interface_property master CMSIS_SVD_VARIABLES ""
set_interface_property master SVD_ADDRESS_GROUP ""

add_interface_port master avl_address address Output 32
add_interface_port master avl_read read Output 1
add_interface_port master avl_write write Output 1
add_interface_port master avl_readdata readdata Input 32
add_interface_port master avl_writedata writedata Output 32
add_interface_port master avl_waitrequest waitrequest Input 1
add_interface_port master avl_byteenable byteenable Output 4
add_interface_port master avl_lock lock Output 1
add_interface_port master avl_response response Input 2


# 
# connection point interrupt_receiver
# 
add_interface interrupt_receiver interrupt start
set_interface_property interrupt_receiver associatedAddressablePoint ""
set_interface_property interrupt_receiver associatedClock clock_sink
set_interface_property interrupt_receiver associatedReset reset_sink
set_interface_property interrupt_receiver irqScheme INDIVIDUAL_REQUESTS
set_interface_property interrupt_receiver ENABLED true
set_interface_property interrupt_receiver EXPORT_OF ""
set_interface_property interrupt_receiver PORT_NAME_MAP ""
set_interface_property interrupt_receiver CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_receiver SVD_ADDRESS_GROUP ""

add_interface_port interrupt_receiver avl_irq irq Input 1


# 
# connection point reset_sink
# 
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""

add_interface_port reset_sink rst_n reset_n Input 1


# 
# connection point smp
# 
add_interface smp conduit end
set_interface_property smp associatedClock clock_sink
set_interface_property smp associatedReset reset_sink
set_interface_property smp ENABLED true
set_interface_property smp EXPORT_OF ""
set_interface_property smp PORT_NAME_MAP ""
set_interface_property smp CMSIS_SVD_VARIABLES ""
set_interface_property smp SVD_ADDRESS_GROUP ""

add_interface_port smp step step Input 1
add_interface_port smp cpu_halt halt Input 1
add_interface_port smp cpu_alive cpu_alive Output 1
add_interface_port smp cpu_halted cpu_halted Output 1
add_interface_port smp breakpoint breakpoint Output 1