# TCL File Generated by Component Editor 20.1
# Sat Sep 30 05:49:44 GMT 2023
# DO NOT MODIFY


# 
# core "ARM810 CPU" v1.0
#  2023.09.30.05:49:43
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module core
# 
set_module_property DESCRIPTION ""
set_module_property NAME core
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "ARM810 CPU"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL core
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file core.sv SYSTEM_VERILOG PATH rtl/core/core.sv TOP_LEVEL_FILE
add_fileset_file arm810.sv SYSTEM_VERILOG PATH rtl/core/arm810.sv
add_fileset_file mul.sv SYSTEM_VERILOG PATH rtl/core/mul.sv
add_fileset_file psr.sv SYSTEM_VERILOG PATH rtl/core/psr.sv
add_fileset_file shifter.sv SYSTEM_VERILOG PATH rtl/core/shifter.sv
add_fileset_file uarch.sv SYSTEM_VERILOG PATH rtl/core/uarch.sv
add_fileset_file add.sv SYSTEM_VERILOG PATH rtl/core/alu/add.sv
add_fileset_file alu.sv SYSTEM_VERILOG PATH rtl/core/alu/alu.sv
add_fileset_file and.sv SYSTEM_VERILOG PATH rtl/core/alu/and.sv
add_fileset_file orr.sv SYSTEM_VERILOG PATH rtl/core/alu/orr.sv
add_fileset_file xor.sv SYSTEM_VERILOG PATH rtl/core/alu/xor.sv
add_fileset_file branch.sv SYSTEM_VERILOG PATH rtl/core/control/branch.sv
add_fileset_file control.sv SYSTEM_VERILOG PATH rtl/core/control/control.sv
add_fileset_file coproc.sv SYSTEM_VERILOG PATH rtl/core/control/coproc.sv
add_fileset_file cycles.sv SYSTEM_VERILOG PATH rtl/core/control/cycles.sv
add_fileset_file data.sv SYSTEM_VERILOG PATH rtl/core/control/data.sv
add_fileset_file debug.sv SYSTEM_VERILOG PATH rtl/core/control/debug.sv
add_fileset_file exception.sv SYSTEM_VERILOG PATH rtl/core/control/exception.sv
add_fileset_file issue.sv SYSTEM_VERILOG PATH rtl/core/control/issue.sv
add_fileset_file mul_fu.sv SYSTEM_VERILOG PATH rtl/core/control/mul_fu.sv
add_fileset_file select.sv SYSTEM_VERILOG PATH rtl/core/control/select.sv
add_fileset_file stall.sv SYSTEM_VERILOG PATH rtl/core/control/stall.sv
add_fileset_file status.sv SYSTEM_VERILOG PATH rtl/core/control/status.sv
add_fileset_file writeback.sv SYSTEM_VERILOG PATH rtl/core/control/writeback.sv
add_fileset_file ldst.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/ldst.sv
add_fileset_file pop.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/pop.sv
add_fileset_file sizes.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/sizes.sv
add_fileset_file cache_ops.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_ops.sv
add_fileset_file cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_lockdown.sv
add_fileset_file cp15.sv SYSTEM_VERILOG PATH rtl/core/cp15/cp15.sv
add_fileset_file cpuid.sv SYSTEM_VERILOG PATH rtl/core/cp15/cpuid.sv
add_fileset_file cyclecnt.sv SYSTEM_VERILOG PATH rtl/core/cp15/cyclecnt.sv
add_fileset_file domain.sv SYSTEM_VERILOG PATH rtl/core/cp15/domain.sv
add_fileset_file far.sv SYSTEM_VERILOG PATH rtl/core/cp15/far.sv
add_fileset_file fsr.sv SYSTEM_VERILOG PATH rtl/core/cp15/fsr.sv
add_fileset_file map.sv SYSTEM_VERILOG PATH rtl/core/cp15/map.sv
add_fileset_file syscfg.sv SYSTEM_VERILOG PATH rtl/core/cp15/syscfg.sv
add_fileset_file tlb.sv SYSTEM_VERILOG PATH rtl/core/cp15/tlb.sv
add_fileset_file tlb_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/tlb_lockdown.sv
add_fileset_file ttbr.sv SYSTEM_VERILOG PATH rtl/core/cp15/ttbr.sv
add_fileset_file branch_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/branch_dec.sv
add_fileset_file coproc_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/coproc_dec.sv
add_fileset_file data_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/data_dec.sv
add_fileset_file decode.sv SYSTEM_VERILOG PATH rtl/core/decode/decode.sv
add_fileset_file isa.sv SYSTEM_VERILOG PATH rtl/core/decode/isa.sv
add_fileset_file mrs.sv SYSTEM_VERILOG PATH rtl/core/decode/mrs.sv
add_fileset_file msr.sv SYSTEM_VERILOG PATH rtl/core/decode/msr.sv
add_fileset_file mul_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/mul_dec.sv
add_fileset_file mux.sv SYSTEM_VERILOG PATH rtl/core/decode/mux.sv
add_fileset_file snd.sv SYSTEM_VERILOG PATH rtl/core/decode/snd.sv
add_fileset_file addr.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/addr.sv
add_fileset_file misc.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/misc.sv
add_fileset_file multiple.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/multiple.sv
add_fileset_file single.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/single.sv
add_fileset_file fetch.sv SYSTEM_VERILOG PATH rtl/core/fetch/fetch.sv
add_fileset_file prefetch.sv SYSTEM_VERILOG PATH rtl/core/fetch/prefetch.sv
add_fileset_file arbiter.sv SYSTEM_VERILOG PATH rtl/core/mmu/arbiter.sv
add_fileset_file fault.sv SYSTEM_VERILOG PATH rtl/core/mmu/fault.sv
add_fileset_file format.sv SYSTEM_VERILOG PATH rtl/core/mmu/format.sv
add_fileset_file mmu.sv SYSTEM_VERILOG PATH rtl/core/mmu/mmu.sv
add_fileset_file pagewalk.sv SYSTEM_VERILOG PATH rtl/core/mmu/pagewalk.sv
add_fileset_file conds.sv SYSTEM_VERILOG PATH rtl/core/porch/conds.sv
add_fileset_file porch.sv SYSTEM_VERILOG PATH rtl/core/porch/porch.sv
add_fileset_file file.sv SYSTEM_VERILOG PATH rtl/core/regs/file.sv
add_fileset_file reg_map.sv SYSTEM_VERILOG PATH rtl/core/regs/reg_map.sv
add_fileset_file regs.sv SYSTEM_VERILOG PATH rtl/core/regs/regs.sv


# 
# parameters
# 


# 
# display items
# 


# 
# connection point clock_sink
# 
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""

add_interface_port clock_sink clk clk Input 1


# 
# connection point master
# 
add_interface master avalon start
set_interface_property master addressUnits SYMBOLS
set_interface_property master associatedClock clock_sink
set_interface_property master associatedReset reset_sink
set_interface_property master bitsPerSymbol 8
set_interface_property master burstOnBurstBoundariesOnly false
set_interface_property master burstcountUnits WORDS
set_interface_property master doStreamReads false
set_interface_property master doStreamWrites false
set_interface_property master holdTime 0
set_interface_property master linewrapBursts false
set_interface_property master maximumPendingReadTransactions 0
set_interface_property master maximumPendingWriteTransactions 0
set_interface_property master readLatency 0
set_interface_property master readWaitTime 1
set_interface_property master setupTime 0
set_interface_property master timingUnits Cycles
set_interface_property master writeWaitTime 0
set_interface_property master ENABLED true
set_interface_property master EXPORT_OF ""
set_interface_property master PORT_NAME_MAP ""
set_interface_property master CMSIS_SVD_VARIABLES ""
set_interface_property master SVD_ADDRESS_GROUP ""

add_interface_port master avl_address address Output 32
add_interface_port master avl_read read Output 1
add_interface_port master avl_write write Output 1
add_interface_port master avl_readdata readdata Input 32
add_interface_port master avl_writedata writedata Output 32
add_interface_port master avl_waitrequest waitrequest Input 1
add_interface_port master avl_byteenable byteenable Output 4


# 
# connection point interrupt_receiver
# 
add_interface interrupt_receiver interrupt start
set_interface_property interrupt_receiver associatedAddressablePoint ""
set_interface_property interrupt_receiver associatedClock clock_sink
set_interface_property interrupt_receiver associatedReset reset_sink
set_interface_property interrupt_receiver irqScheme INDIVIDUAL_REQUESTS
set_interface_property interrupt_receiver ENABLED true
set_interface_property interrupt_receiver EXPORT_OF ""
set_interface_property interrupt_receiver PORT_NAME_MAP ""
set_interface_property interrupt_receiver CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_receiver SVD_ADDRESS_GROUP ""

add_interface_port interrupt_receiver avl_irq irq Input 1


# 
# connection point reset_sink
# 
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""

add_interface_port reset_sink rst_n reset_n Input 1


# 
# connection point smp
# 
add_interface smp conduit end
set_interface_property smp associatedClock clock_sink
set_interface_property smp associatedReset reset_sink
set_interface_property smp ENABLED true
set_interface_property smp EXPORT_OF ""
set_interface_property smp PORT_NAME_MAP ""
set_interface_property smp CMSIS_SVD_VARIABLES ""
set_interface_property smp SVD_ADDRESS_GROUP ""

add_interface_port smp step step Input 1
add_interface_port smp cpu_halt halt Input 1
add_interface_port smp cpu_halted cpu_halted Output 1
add_interface_port smp breakpoint breakpoint Output 1