# TCL File Generated by Component Editor 20.1 # Sun Sep 04 22:05:36 GMT 2022 # DO NOT MODIFY # # conspiracion_bus_master "Toplevel bus master" v1.0 # 2022.09.04.22:05:36 # # # # request TCL package from ACDS 16.1 # package require -exact qsys 16.1 # # module conspiracion_bus_master # set_module_property DESCRIPTION "" set_module_property NAME conspiracion_bus_master set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property AUTHOR "" set_module_property DISPLAY_NAME "Toplevel bus master" set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false set_module_property REPORT_HIERARCHY false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL bus_master set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file master.sv SYSTEM_VERILOG PATH rtl/bus/master.sv TOP_LEVEL_FILE # # parameters # # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point avalon_master # add_interface avalon_master avalon start set_interface_property avalon_master addressUnits SYMBOLS set_interface_property avalon_master associatedClock clock set_interface_property avalon_master associatedReset reset_sink set_interface_property avalon_master bitsPerSymbol 8 set_interface_property avalon_master burstOnBurstBoundariesOnly false set_interface_property avalon_master burstcountUnits WORDS set_interface_property avalon_master doStreamReads false set_interface_property avalon_master doStreamWrites false set_interface_property avalon_master holdTime 0 set_interface_property avalon_master linewrapBursts false set_interface_property avalon_master maximumPendingReadTransactions 0 set_interface_property avalon_master maximumPendingWriteTransactions 0 set_interface_property avalon_master readLatency 0 set_interface_property avalon_master readWaitTime 1 set_interface_property avalon_master setupTime 0 set_interface_property avalon_master timingUnits Cycles set_interface_property avalon_master writeWaitTime 0 set_interface_property avalon_master ENABLED true set_interface_property avalon_master EXPORT_OF "" set_interface_property avalon_master PORT_NAME_MAP "" set_interface_property avalon_master CMSIS_SVD_VARIABLES "" set_interface_property avalon_master SVD_ADDRESS_GROUP "" add_interface_port avalon_master avl_address address Output 32 add_interface_port avalon_master avl_read read Output 1 add_interface_port avalon_master avl_readdata readdata Input 32 add_interface_port avalon_master avl_write write Output 1 add_interface_port avalon_master avl_writedata writedata Output 32 add_interface_port avalon_master avl_byteenable byteenable Output 4 add_interface_port avalon_master avl_waitrequest waitrequest Input 1 # # connection point reset_sink # add_interface reset_sink reset end set_interface_property reset_sink associatedClock clock set_interface_property reset_sink synchronousEdges DEASSERT set_interface_property reset_sink ENABLED true set_interface_property reset_sink EXPORT_OF "" set_interface_property reset_sink PORT_NAME_MAP "" set_interface_property reset_sink CMSIS_SVD_VARIABLES "" set_interface_property reset_sink SVD_ADDRESS_GROUP "" add_interface_port reset_sink rst reset Input 1 # # connection point core # add_interface core conduit end set_interface_property core associatedClock clock set_interface_property core associatedReset reset_sink set_interface_property core ENABLED true set_interface_property core EXPORT_OF "" set_interface_property core PORT_NAME_MAP "" set_interface_property core CMSIS_SVD_VARIABLES "" set_interface_property core SVD_ADDRESS_GROUP "" add_interface_port core addr addr Input 30 add_interface_port core data_rd data_rd Output 32 add_interface_port core data_rw data_rw Input 32 add_interface_port core ready ready Output 1 add_interface_port core write write Input 1 add_interface_port core start start Input 1