# -------------------------------------------------------------------------- # # # Copyright (C) 2020 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details, at # https://fpgasoftware.intel.com/eula. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition # Date created = 14:48:15 September 01, 2022 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # conspiracion_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEMA5F31C6 set_global_assignment -name TOP_LEVEL_ENTITY conspiracion set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:48:15 SEPTEMBER 01, 2022" set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck -tag __hps_sdram_p0 set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck_n -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[0] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[1] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[2] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[3] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[4] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[5] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[6] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[7] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dm -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs_n -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[0] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[10] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[11] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[12] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[1] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[2] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[3] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[4] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[5] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[6] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[7] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[8] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[9] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[0] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[1] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[2] -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cas_n -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cke -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cs_n -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_odt -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ras_n -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_we_n -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_reset_n -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck -tag __hps_sdram_p0 set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck_n -tag __hps_sdram_p0 set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0 set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0 set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0 set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0 set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0 set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to plat|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0 set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to plat|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0 set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name ECO_REGENERATE_REPORT ON set_location_assignment PIN_AF14 -to clk_clk set_location_assignment PIN_AB12 -to rst_n set_location_assignment PIN_AC12 -to halt set_location_assignment PIN_V16 -to pio_leds[0] set_location_assignment PIN_W16 -to pio_leds[1] set_location_assignment PIN_V17 -to pio_leds[2] set_location_assignment PIN_V18 -to pio_leds[3] set_location_assignment PIN_W17 -to pio_leds[4] set_location_assignment PIN_W19 -to pio_leds[5] set_location_assignment PIN_Y19 -to pio_leds[6] set_location_assignment PIN_W20 -to pio_leds[7] set_location_assignment PIN_AA14 -to pio_buttons set_location_assignment PIN_AD11 -to pio_switches[0] set_location_assignment PIN_AD12 -to pio_switches[1] set_location_assignment PIN_AE11 -to pio_switches[2] set_location_assignment PIN_AC9 -to pio_switches[3] set_location_assignment PIN_AD10 -to pio_switches[4] set_location_assignment PIN_AE12 -to pio_switches[5] set_location_assignment PIN_A11 -to vga_dac_clk set_location_assignment PIN_B11 -to vga_dac_hsync set_location_assignment PIN_D11 -to vga_dac_vsync set_location_assignment PIN_F10 -to vga_dac_blank_n set_location_assignment PIN_C10 -to vga_dac_sync_n set_location_assignment PIN_A13 -to vga_dac_r[0] set_location_assignment PIN_C13 -to vga_dac_r[1] set_location_assignment PIN_E13 -to vga_dac_r[2] set_location_assignment PIN_B12 -to vga_dac_r[3] set_location_assignment PIN_C12 -to vga_dac_r[4] set_location_assignment PIN_D12 -to vga_dac_r[5] set_location_assignment PIN_E12 -to vga_dac_r[6] set_location_assignment PIN_F13 -to vga_dac_r[7] set_location_assignment PIN_J9 -to vga_dac_g[0] set_location_assignment PIN_J10 -to vga_dac_g[1] set_location_assignment PIN_H12 -to vga_dac_g[2] set_location_assignment PIN_G10 -to vga_dac_g[3] set_location_assignment PIN_G11 -to vga_dac_g[4] set_location_assignment PIN_G12 -to vga_dac_g[5] set_location_assignment PIN_F11 -to vga_dac_g[6] set_location_assignment PIN_E11 -to vga_dac_g[7] set_location_assignment PIN_B13 -to vga_dac_b[0] set_location_assignment PIN_G13 -to vga_dac_b[1] set_location_assignment PIN_H13 -to vga_dac_b[2] set_location_assignment PIN_F14 -to vga_dac_b[3] set_location_assignment PIN_H14 -to vga_dac_b[4] set_location_assignment PIN_F15 -to vga_dac_b[5] set_location_assignment PIN_G15 -to vga_dac_b[6] set_location_assignment PIN_J14 -to vga_dac_b[7] set_location_assignment PIN_AK14 -to vram_wire_addr[0] set_location_assignment PIN_AH14 -to vram_wire_addr[1] set_location_assignment PIN_AG15 -to vram_wire_addr[2] set_location_assignment PIN_AE14 -to vram_wire_addr[3] set_location_assignment PIN_AB15 -to vram_wire_addr[4] set_location_assignment PIN_AC14 -to vram_wire_addr[5] set_location_assignment PIN_AD14 -to vram_wire_addr[6] set_location_assignment PIN_AF15 -to vram_wire_addr[7] set_location_assignment PIN_AH15 -to vram_wire_addr[8] set_location_assignment PIN_AG13 -to vram_wire_addr[9] set_location_assignment PIN_AG12 -to vram_wire_addr[10] set_location_assignment PIN_AH13 -to vram_wire_addr[11] set_location_assignment PIN_AJ14 -to vram_wire_addr[12] set_location_assignment PIN_AF13 -to vram_wire_ba[0] set_location_assignment PIN_AJ12 -to vram_wire_ba[1] set_location_assignment PIN_AF11 -to vram_wire_cas_n set_location_assignment PIN_AK13 -to vram_wire_cke set_location_assignment PIN_AH12 -to vram_wire_clk set_location_assignment PIN_AG11 -to vram_wire_cs_n set_location_assignment PIN_AK6 -to vram_wire_dq[0] set_location_assignment PIN_AJ7 -to vram_wire_dq[1] set_location_assignment PIN_AK7 -to vram_wire_dq[2] set_location_assignment PIN_AK8 -to vram_wire_dq[3] set_location_assignment PIN_AK9 -to vram_wire_dq[4] set_location_assignment PIN_AG10 -to vram_wire_dq[5] set_location_assignment PIN_AK11 -to vram_wire_dq[6] set_location_assignment PIN_AJ11 -to vram_wire_dq[7] set_location_assignment PIN_AH10 -to vram_wire_dq[8] set_location_assignment PIN_AJ10 -to vram_wire_dq[9] set_location_assignment PIN_AJ9 -to vram_wire_dq[10] set_location_assignment PIN_AH9 -to vram_wire_dq[11] set_location_assignment PIN_AH8 -to vram_wire_dq[12] set_location_assignment PIN_AH7 -to vram_wire_dq[13] set_location_assignment PIN_AJ6 -to vram_wire_dq[14] set_location_assignment PIN_AJ5 -to vram_wire_dq[15] set_location_assignment PIN_AB13 -to vram_wire_dqm[0] set_location_assignment PIN_AK12 -to vram_wire_dqm[1] set_location_assignment PIN_AE13 -to vram_wire_ras_n set_location_assignment PIN_AA13 -to vram_wire_we_n set_global_assignment -name SEARCH_PATH rtl set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/and.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/branch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/control.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/coproc.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/cycles.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/data.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/debug.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/exception.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/issue.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/mul.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/ldst.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/pop.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/sizes.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/psr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/select.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/stall.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/writeback.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cp15.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cpuid.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/map.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/coproc.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/isa.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/mrs.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/msr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/mul.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/mux.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/addr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/misc.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/multiple.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/single.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/snd.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/arbiter.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mul.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/conds.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/porch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/map.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/shifter.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv set_global_assignment -name QSYS_FILE platform.qsys set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv set_global_assignment -name QIP_FILE platform/synthesis/platform.qip set_global_assignment -name SDC_FILE conspiracion.sdc set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_oct_rzqin -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[0] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[1] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[2] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[3] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[4] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[5] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[6] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[7] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs_n -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck_n -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck_n -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[0] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[0] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[10] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[10] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[11] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[11] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[12] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[12] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[1] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[1] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[2] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[2] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[3] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[3] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[4] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[4] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[5] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[5] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[6] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[6] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[7] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[7] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[8] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[8] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[9] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[9] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[0] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[0] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[1] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[1] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[2] -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[2] -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cas_n -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cas_n -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cke -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cke -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cs_n -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cs_n -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_odt -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_odt -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ras_n -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ras_n -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_we_n -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_we_n -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_reset_n -tag __hps_sdram_p0 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_reset_n -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm -tag __hps_sdram_p0 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm -tag __hps_sdram_p0 set_global_assignment -name QIP_FILE ip/dsp_mul.qip set_global_assignment -name SIP_FILE ip/dsp_mul.sip set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE bus_test.stp set_global_assignment -name SIGNALTAP_FILE bus_test.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top