From 5d8c9e67b1b37679823192201900507c3ba15d5b Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 9 Nov 2022 08:25:40 -0600
Subject: Add reset signal to bus master

---
 tb/platform.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tb')

diff --git a/tb/platform.sv b/tb/platform.sv
index 16c66cb..8470979 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -62,7 +62,7 @@ module platform
 	bus_master master_0
 	(
 		.clk(clk_clk),
-		.rst(!reset_reset_n),
+		.rst_n(!reset_reset_n),
 		.addr(master_0_core_addr),
 		.start(master_0_core_start),
 		.write(master_0_core_write),
-- 
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