From 4dc4e712b21fcf08143005a56b1501f53c127a67 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 18 Sep 2022 17:17:02 -0600 Subject: Fix public_flat_rw signals --- tb/platform.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tb') diff --git a/tb/platform.sv b/tb/platform.sv index 10df2e0..7c2ef90 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -28,9 +28,9 @@ module platform ( logic[31:0] avl_address /*verilator public*/; logic avl_read /*verilator public*/; logic avl_write /*verilator public*/; - logic[31:0] avl_readdata /*verilator public*/; + logic[31:0] avl_readdata /*verilator public_flat_rw @(negedge clk_clk)*/; logic[31:0] avl_writedata /*verilator public*/; - logic avl_waitrequest /*verilator public*/; + logic avl_waitrequest /*verilator public_flat_rw @(negedge clk_clk)*/; logic[3:0] avl_byteenable /*verilator public*/; bus_master master_0 -- cgit v1.2.3