From 0c63c46e31642d0102542a745af6b445a9d22b3b Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 13 Dec 2022 21:43:25 -0600 Subject: Implement interrupt controller --- tb/vga_domain.sv | 1 + 1 file changed, 1 insertion(+) (limited to 'tb/vga_domain.sv') diff --git a/tb/vga_domain.sv b/tb/vga_domain.sv index d3ffbc0..0c9aac5 100644 --- a/tb/vga_domain.sv +++ b/tb/vga_domain.sv @@ -7,6 +7,7 @@ module vga_domain logic[25:0] avl_address /*verilator public*/; logic avl_read /*verilator public*/; logic avl_write /*verilator public*/; + logic avl_irq /*verilator public_flat_rw @(negedge clk_clk)*/; logic[15:0] avl_readdata /*verilator public_flat_rw @(negedge clk_clk)*/; logic[31:0] avl_writedata /*verilator public*/; logic avl_waitrequest /*verilator public_flat_rw @(negedge clk_clk)*/; -- cgit v1.2.3