From 8c7b6113c51215de9f57f016681bfcc43513ee37 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 25 Sep 2022 20:31:25 -0600
Subject: Rename HPS SDRAM testbench file

---
 tb/top/hps_sdram_test.cpp | 93 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 tb/top/hps_sdram_test.cpp

(limited to 'tb/top/hps_sdram_test.cpp')

diff --git a/tb/top/hps_sdram_test.cpp b/tb/top/hps_sdram_test.cpp
new file mode 100644
index 0000000..b173c41
--- /dev/null
+++ b/tb/top/hps_sdram_test.cpp
@@ -0,0 +1,93 @@
+#include <cstdio>
+
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+
+#include "Vhps_sdram_test.h"
+#include "Vhps_sdram_test_hps_sdram_test.h"
+#include "Vhps_sdram_test_platform.h"
+
+#include "../avalon.hpp"
+#include "../mem.hpp"
+
+int main(int argc, char **argv)
+{
+	using namespace taller::avalon;
+
+    Verilated::commandArgs(argc, argv);
+
+	Vhps_sdram_test top;
+
+#ifdef TRACE
+	Verilated::traceEverOn(true);
+	VerilatedVcdC trace;
+
+	top.trace(&trace, 0);
+	trace.open("trace.vcd");
+#endif
+
+	interconnect<Vhps_sdram_test_platform> avl(*top.hps_sdram_test->plat);
+	mem hps_ddr3(0x0000'0000, 512 << 20);
+
+	avl.attach(hps_ddr3);
+
+	int time = 0;
+	top.clk_clk = 1;
+
+	auto tick = [&]()
+	{
+		top.clk_clk = !top.clk_clk;
+		top.eval();
+		avl.tick(top.clk_clk);
+#ifdef TRACE
+		trace.dump(time++);
+#endif
+	};
+
+	auto cycle = [&]()
+	{
+		tick();
+		tick();
+		std::printf("[%02d] out=0x%02x, done=%d\n", time, top.out, top.done);
+	};
+
+	auto io = [&]()
+	{
+		top.io = 0;
+		cycle();
+		top.io = 1;
+		for(int i = 0; i < 4; ++i)
+		{
+			cycle();
+		}
+	};
+
+	top.dir = 1;
+	top.io = 1;
+	top.mov = 1;
+	top.clr = 1;
+
+	for(int i = 0; i < 5; ++i)
+	{
+		top.add = 0;
+		cycle();
+		top.add = 1;
+		cycle();
+	}
+
+	io();
+
+	top.clr = 0;
+	cycle();
+	top.clr = 1;
+	cycle();
+
+	top.dir = 0;
+	io();
+
+#ifdef TRACE
+	trace.close();
+#endif
+
+    top.final();
+}
-- 
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