From 2c6998db4ad3b663fa32384739bc11930be5afa2 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 2 Oct 2023 16:47:23 -0600 Subject: tb: implement verilated slaves --- tb/sim_slave.sv | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 tb/sim_slave.sv (limited to 'tb/sim_slave.sv') diff --git a/tb/sim_slave.sv b/tb/sim_slave.sv new file mode 100644 index 0000000..1598701 --- /dev/null +++ b/tb/sim_slave.sv @@ -0,0 +1,28 @@ +module sim_slave +( + input logic clk, + + input logic waitrequest, + input logic[31:0] readdata, + output logic[31:0] address, + writedata, + output logic read, + write +); + + logic[31:0] avl_address /*verilator public_flat_rw @(negedge clk)*/; + logic avl_read /*verilator public_flat_rw @(negedge clk)*/; + logic avl_write /*verilator public_flat_rw @(negedge clk)*/; + logic[31:0] avl_readdata /*verilator public*/; + logic[31:0] avl_writedata /*verilator public_flat_rw @(negedge clk)*/; + logic avl_waitrequest /*verilator public*/; + + assign read = avl_read; + assign write = avl_write; + assign address = avl_address; + assign writedata = avl_writedata; + + assign avl_readdata = readdata; + assign avl_waitrequest = waitrequest; + +endmodule -- cgit v1.2.3