From d006be2e89aa493237f212811ee880ed8b54241b Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 11 Dec 2022 17:28:03 -0600 Subject: Implement MMU access checks --- tb/sim/paging.S | 6 +++++- tb/sim/paging.py | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'tb/sim') diff --git a/tb/sim/paging.S b/tb/sim/paging.S index b1dee0e..e67e163 100644 --- a/tb/sim/paging.S +++ b/tb/sim/paging.S @@ -2,6 +2,8 @@ data_abort: mrc p15, 0, r2, c6, c0, 0 mrc p15, 0, r3, c5, c0, 0 + # Domain field is invalid for section translation faults + and r3, r3, #0b1111 mov pc, r4 .global reset @@ -30,8 +32,10 @@ reset: ldr r2, =0x00003002 str r2, [r1], #4 - # Set translation base and enable MMU + # Set translation base, domain control register and enable MMU mov r1, #(1 << 0) + mov r2, #-1 + mcr p15, 0, r2, c3, c0, 0 mcr p15, 0, r0, c2, c0, 0 mcr p15, 0, r1, c1, c0, 0 diff --git a/tb/sim/paging.py b/tb/sim/paging.py index 2249be0..e687051 100644 --- a/tb/sim/paging.py +++ b/tb/sim/paging.py @@ -4,5 +4,5 @@ def final(): assert_reg(r0, 0x01234567) assert_reg(r1, 0x89abcdef) assert_reg(r2, 0x89abcde0) - assert_reg(r3, 0) + assert_reg(r3, 0b0101) # Section translation fault, p. 720 assert_reg(r4, read_reg(r5)) -- cgit v1.2.3