From 87c73314d7ce0062b13ae14f376ec50a4653fb18 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 16 Oct 2022 18:20:45 -0600
Subject: Implement register dumps

---
 tb/sim/hazards.py |  3 ++-
 tb/sim/sim.py     | 14 +++++++++++++-
 2 files changed, 15 insertions(+), 2 deletions(-)

(limited to 'tb/sim')

diff --git a/tb/sim/hazards.py b/tb/sim/hazards.py
index 9fa3e44..b89b15b 100644
--- a/tb/sim/hazards.py
+++ b/tb/sim/hazards.py
@@ -1,9 +1,10 @@
 SP = 256
 
+cycles = 256
 mem_dumps = [range(SP - 4, SP)]
 
 def final():
     assert_reg(r0, 59)
     assert_reg(r1, 0)
-    assert_reg(sp, SP)
+    assert_reg(sp_svc, SP)
     assert_mem(SP - 4, 3)
diff --git a/tb/sim/sim.py b/tb/sim/sim.py
index 9a239e9..dd0f72e 100755
--- a/tb/sim/sim.py
+++ b/tb/sim/sim.py
@@ -33,6 +33,12 @@ all_regs = {
     'r12_usr': 'r12_usr',
     'r12_fiq': 'r12_fiq',
     'sp': 'r13_usr',
+    'sp_usr': 'r13_usr',
+    'sp_svc': 'r13_svc',
+    'sp_abt': 'r13_abt',
+    'sp_und': 'r13_und',
+    'sp_irq': 'r13_irq',
+    'sp_fiq': 'r13_fiq',
     'r13': 'r13_usr',
     'r13_usr': 'r13_usr',
     'r13_svc': 'r13_svc',
@@ -41,6 +47,12 @@ all_regs = {
     'r13_irq': 'r13_irq',
     'r13_fiq': 'r13_fiq',
     'lr': 'r14_usr',
+    'lr_usr': 'r14_usr',
+    'lr_svc': 'r14_svc',
+    'lr_abt': 'r14_abt',
+    'lr_und': 'r14_und',
+    'lr_irq': 'r14_irq',
+    'lr_fiq': 'r14_fiq',
     'r14': 'r14_usr',
     'r14_usr': 'r14_usr',
     'r14_svc': 'r14_svc',
@@ -166,4 +178,4 @@ for line in output.stdout.split('\n'):
 if final := module_get('final'):
     final()
 
-print(f'Test \'{test_name}\' passed', file=sys.stderr)
+print(f'\033[32mTest \'\033[33;1m{test_name}\033[0m\033[32m\' passed\033[0m', file=sys.stderr)
-- 
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