From 6ebe514137fa41ac015122da4dcaba56af84e531 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 19 Nov 2022 21:19:18 -0600 Subject: Implement JTAG-UART input --- tb/sim/sim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tb/sim') diff --git a/tb/sim/sim.py b/tb/sim/sim.py index b14e0fd..91fc348 100755 --- a/tb/sim/sim.py +++ b/tb/sim/sim.py @@ -249,7 +249,7 @@ mem_dumps = module_get('mem_dumps', []) if init := module_get('init'): init() -exec_args = [verilated, '--headless', '--cycles', str(cycles), '--dump-regs'] +exec_args = [verilated, '--headless', '--no-tty', '--cycles', str(cycles), '--dump-regs'] for rng in mem_dumps: length = rng.stop - rng.start -- cgit v1.2.3