From 1ea0519a2b6b81e0ba324cd69f8785735e7cbef5 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 8 Nov 2022 21:33:59 -0600
Subject: Fix handling of multi-cycle Avalon waitrequest states in bus master

---
 tb/sim/fibonacci.py | 2 +-
 tb/sim/sdram.py     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'tb/sim')

diff --git a/tb/sim/fibonacci.py b/tb/sim/fibonacci.py
index fb20b63..f8bec8a 100644
--- a/tb/sim/fibonacci.py
+++ b/tb/sim/fibonacci.py
@@ -1,7 +1,7 @@
 BASE = 0x0001_0000
 COUNT = 20
 
-cycles = 500
+cycles = 1024
 mem_dumps = [range(BASE, BASE + 4 * COUNT)]
 
 def final():
diff --git a/tb/sim/sdram.py b/tb/sim/sdram.py
index 2225941..fbc2c97 100644
--- a/tb/sim/sdram.py
+++ b/tb/sim/sdram.py
@@ -1,7 +1,7 @@
 START = 0x0000_1000
 END   = 0x0000_2000
 
-cycles = 15000
+cycles = 30000
 mem_dumps = [range(START, END)]
 
 def final():
-- 
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