From d6fff0eb1ce867192d30babb839fc09c30049f0b Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 7 Dec 2022 20:59:22 -0600
Subject: Fix register-indirect shifts

---
 tb/sim/shifts.py | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tb/sim/shifts.py')

diff --git a/tb/sim/shifts.py b/tb/sim/shifts.py
index 38f24a2..9923124 100644
--- a/tb/sim/shifts.py
+++ b/tb/sim/shifts.py
@@ -2,3 +2,4 @@ def final():
 	assert_reg(r0, 0x00015000)
 	assert_reg(r2, 0x00015000)
 	assert_reg(r3, 0xaaa9fd55)
+	assert_reg(r4, 0)
-- 
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