From 683352ce030923bdef3cf4fe90d6cb73f4f74529 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 16 Nov 2022 16:46:52 -0600
Subject: Implement psr read/write logic

---
 tb/sim/modeswitch.py | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

(limited to 'tb/sim/modeswitch.py')

diff --git a/tb/sim/modeswitch.py b/tb/sim/modeswitch.py
index 6919f2e..6c8cd79 100644
--- a/tb/sim/modeswitch.py
+++ b/tb/sim/modeswitch.py
@@ -1,3 +1,10 @@
 def final():
-    #TODO
-    assert_reg(r0, -1)
+    assert_reg(r0, 0x0000_01d3)
+    assert_reg(r1, 0x0000_01d3)
+    assert_reg(r2, 0x0000_01d3)
+    assert_reg(r3, 0x0000_0010)
+    assert_reg(r4, 0x0000_0110)
+    assert_reg(r5, 0x4000_0110)
+    assert_reg(cpsr, 0x0000_0110)
+    assert_reg(r13_svc, 0x2000_0000)
+    assert_reg(r13_und, 0x0000_01db)
-- 
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