From b762fc978a49910986e00e6c08e0afbe1e612858 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 18 Sep 2022 19:07:24 -0600 Subject: Rename data_rw to data_wr in bus master --- tb/platform.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tb/platform.sv') diff --git a/tb/platform.sv b/tb/platform.sv index 7c2ef90..3d2521b 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -2,7 +2,7 @@ module platform ( input wire clk_clk, // clk.clk input wire [29:0] master_0_core_addr /*verilator public*/,// master_0_core.addr output wire [31:0] master_0_core_data_rd /*verilator public*/,// .data_rd - input wire [31:0] master_0_core_data_rw /*verilator public*/,// .data_rw + input wire [31:0] master_0_core_data_wr /*verilator public*/,// .data_wr output wire master_0_core_ready /*verilator public*/,// .ready input wire master_0_core_write /*verilator public*/,// .write input wire master_0_core_start /*verilator public*/,// .start @@ -42,7 +42,7 @@ module platform ( .write(master_0_core_write), .ready(master_0_core_ready), .data_rd(master_0_core_data_rd), - .data_rw(master_0_core_data_rw), + .data_wr(master_0_core_data_wr), .* ); -- cgit v1.2.3