From 1c1620e48ff6b807aed0c955792b4e8a17614c20 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 9 Nov 2022 09:54:13 -0600 Subject: Implement initial state randomization in sim --- tb/platform.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tb/platform.sv') diff --git a/tb/platform.sv b/tb/platform.sv index a2820fa..a43af19 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -30,7 +30,7 @@ module platform input wire memory_oct_rzqin, // .oct_rzqin output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export output wire pll_0_outclk3_clk, // pll_0_outclk3.clk - input wire reset_reset_n, // reset.reset_n + input wire reset_reset_n /*verilator public*/,// reset.reset_n output wire [12:0] vram_wire_addr, // vram_wire.addr output wire [1:0] vram_wire_ba, // .ba output wire vram_wire_cas_n, // .cas_n -- cgit v1.2.3