From d4d9f5296b193f80ee7fc2e42e52d974249d09e0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 24 Sep 2023 23:39:17 -0600
Subject: tb: implement support for cache line-sized slaves

---
 tb/mem.cpp | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 tb/mem.cpp

(limited to 'tb/mem.cpp')

diff --git a/tb/mem.cpp b/tb/mem.cpp
new file mode 100644
index 0000000..47073ab
--- /dev/null
+++ b/tb/mem.cpp
@@ -0,0 +1,50 @@
+#include <cassert>
+#include <cstdint>
+#include <memory>
+
+#include "avalon.hpp"
+#include "mem.hpp"
+
+namespace taller::avalon
+{
+	mem::mem(std::uint32_t base, std::uint32_t size)
+	: slave(base, size, 4),
+	  block(std::make_unique<line[]>(size >> 4))
+	{}
+
+	bool mem::read_line(std::uint32_t addr, line &data)
+	{
+		data = block[addr];
+		return true;/*ready();*/
+	}
+
+	bool mem::write_line(std::uint32_t addr, const line &data, unsigned byte_enable)
+	{
+		for (unsigned i = 0; i < 4; ++i) {
+			std::uint32_t bytes = 0;
+
+			if (byte_enable & 0b1000)
+				bytes |= 0xff << 24;
+
+			if (byte_enable & 0b0100)
+				bytes |= 0xff << 16;
+
+			if (byte_enable & 0b0010)
+				bytes |= 0xff << 8;
+
+			if (byte_enable & 0b0001)
+				bytes |= 0xff;
+
+			byte_enable >>= 4;
+			block[addr].words[i] = (data.words[i] & bytes) | (block[addr].words[i] & ~bytes);
+		}
+
+		return true;/*ready();*/
+	}
+
+	bool mem::ready() noexcept
+	{
+		count = count > 0 ? count - 1 : 2;
+		return count == 0;
+	}
+}
-- 
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