From 1ea0519a2b6b81e0ba324cd69f8785735e7cbef5 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 8 Nov 2022 21:33:59 -0600 Subject: Fix handling of multi-cycle Avalon waitrequest states in bus master --- tb/mem.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'tb/mem.cpp') diff --git a/tb/mem.cpp b/tb/mem.cpp index bfbc3ea..6eeb7df 100644 --- a/tb/mem.cpp +++ b/tb/mem.cpp @@ -16,7 +16,7 @@ namespace taller::avalon bool mem::read(std::uint32_t addr, std::uint32_t &data) { data = block[addr]; - return true; + return ready(); } bool mem::write(std::uint32_t addr, std::uint32_t data, unsigned byte_enable) @@ -44,6 +44,12 @@ namespace taller::avalon } block[addr] = (data & bytes) | (block[addr] & ~bytes); - return true; + return ready(); + } + + bool mem::ready() noexcept + { + count = count > 0 ? count - 1 : 2; + return count == 0; } } -- cgit v1.2.3