From 827c40829903d5b870f47ab2f389792ed10211bd Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 13 Feb 2024 12:14:31 -0600 Subject: rtl/core/control: don't shift branch history registers inside loops --- sim/sim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sim') diff --git a/sim/sim.py b/sim/sim.py index 6ad3d23..494d5c3 100755 --- a/sim/sim.py +++ b/sim/sim.py @@ -152,12 +152,12 @@ def recv_mem_dump(): while_running() out(f'{COLOR_BLUE}{line}{COLOR_RESET}') -def read_mem(base, length, *, may_fail = False): +def read_mem(base, length, *, may_fail=False, phys=False): fragments = [] i = 0 if halted and length > 0: - print('dump-mem', base >> 2, (length + base - (base & ~0b11) + 0b11) >> 2, file=sim_end, flush=True) + print('dump-phys' if phys else 'dump-mem', base >> 2, (length + base - (base & ~0b11) + 0b11) >> 2, file=sim_end, flush=True) recv_mem_dump() while length > 0: -- cgit v1.2.3