From d2be560fa668cefcc5eff6b88180f12fec0c326e Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 14 Dec 2022 19:16:54 -0600
Subject: Fix implementation of MMU access faults

---
 sim/sim.py | 1 +
 1 file changed, 1 insertion(+)

(limited to 'sim/sim.py')

diff --git a/sim/sim.py b/sim/sim.py
index 4a1dfa8..03d45c7 100755
--- a/sim/sim.py
+++ b/sim/sim.py
@@ -72,6 +72,7 @@ all_regs = [
     ('ttbr', 'ttbr'),
     ('far', 'far'),
     ('fsr', 'fsr'),
+    ('dacr', 'dacr'),
     ]
 
 regs = {}
-- 
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