From 0284628a47d5b4797c89f6846b9efee3f1243b94 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 11 Dec 2022 23:00:37 -0600 Subject: Implement register writes from gdb --- sim/sim.py | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'sim/sim.py') diff --git a/sim/sim.py b/sim/sim.py index b4e0882..448c39f 100755 --- a/sim/sim.py +++ b/sim/sim.py @@ -73,6 +73,14 @@ all_regs = [ regs = {} read_reg = lambda r: regs.setdefault(r, 0) +def write_reg(reg, value): + assert halted + + value = unsigned(value) + regs[reg] = value + + print('patch-reg', value, reg, file=sim_end, flush=True) + dumped = [] halted = False @@ -278,6 +286,7 @@ module = importlib.util.module_from_spec(spec) prelude = { 'read_reg': read_reg, + 'write_reg': write_reg, 'read_mem': read_mem, 'write_mem': write_mem, 'assert_reg': assert_reg, -- cgit v1.2.3