From ef151fffb14eac19a19121dfb4c1e015e7470038 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 14 Dec 2022 22:24:58 -0600 Subject: Fix register corruption when interrupting a load-store --- rtl/core/control/ldst/ldst.sv | 3 ++- rtl/core/control/psr.sv | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'rtl') diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index 027fb0a..c8f0dcb 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -105,6 +105,7 @@ module core_control_ldst end mem_start <= !cycle.transfer || (mem_ready && pop_valid); - end + end else if(cycle.escalate) + ldst <= 0; end endmodule diff --git a/rtl/core/control/psr.sv b/rtl/core/control/psr.sv index 07bf4e5..ff9b13f 100644 --- a/rtl/core/control/psr.sv +++ b/rtl/core/control/psr.sv @@ -77,6 +77,7 @@ module core_control_psr psr_wr_control <= 1; exception_spsr <= cpsr_rd; end else if(next_cycle.exception) begin + psr <= 0; psr_saved <= 1; psr_wr_flags <= 1; end else if(next_cycle.psr) -- cgit v1.2.3