From ed0bd705f94f6aea568ec8405534984a37770f21 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 25 Sep 2023 19:12:49 -0600 Subject: rtl/core, tb: replace bus_master with a new top-level module --- rtl/bus_master.sv | 73 ---------------------------------- rtl/core/control/mul.sv | 67 ------------------------------- rtl/core/control/mul_fu.sv | 67 +++++++++++++++++++++++++++++++ rtl/core/control/psr.sv | 81 -------------------------------------- rtl/core/control/status.sv | 81 ++++++++++++++++++++++++++++++++++++++ rtl/core/core.sv | 91 +++++++++++++++++++++++++++++++++++++++++++ rtl/core/decode/branch.sv | 18 --------- rtl/core/decode/branch_dec.sv | 18 +++++++++ rtl/core/decode/coproc.sv | 24 ------------ rtl/core/decode/coproc_dec.sv | 24 ++++++++++++ rtl/core/decode/data.sv | 65 ------------------------------- rtl/core/decode/data_dec.sv | 65 +++++++++++++++++++++++++++++++ rtl/core/decode/mul.sv | 33 ---------------- rtl/core/decode/mul_dec.sv | 33 ++++++++++++++++ rtl/core/regs/map.sv | 30 -------------- rtl/core/regs/reg_map.sv | 30 ++++++++++++++ rtl/top/conspiracion.sv | 47 ++++++---------------- 17 files changed, 420 insertions(+), 427 deletions(-) delete mode 100644 rtl/bus_master.sv delete mode 100644 rtl/core/control/mul.sv create mode 100644 rtl/core/control/mul_fu.sv delete mode 100644 rtl/core/control/psr.sv create mode 100644 rtl/core/control/status.sv create mode 100644 rtl/core/core.sv delete mode 100644 rtl/core/decode/branch.sv create mode 100644 rtl/core/decode/branch_dec.sv delete mode 100644 rtl/core/decode/coproc.sv create mode 100644 rtl/core/decode/coproc_dec.sv delete mode 100644 rtl/core/decode/data.sv create mode 100644 rtl/core/decode/data_dec.sv delete mode 100644 rtl/core/decode/mul.sv create mode 100644 rtl/core/decode/mul_dec.sv delete mode 100644 rtl/core/regs/map.sv create mode 100644 rtl/core/regs/reg_map.sv (limited to 'rtl') diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv deleted file mode 100644 index 0c6af55..0000000 --- a/rtl/bus_master.sv +++ /dev/null @@ -1,73 +0,0 @@ -module bus_master -( - input logic clk, - rst_n, - - input logic[29:0] addr, - input logic start, - write, - output logic ready, - output logic[31:0] data_rd, - input logic[31:0] data_wr, - input logic[3:0] data_be, - output logic cpu_clk, - cpu_rst_n, - irq, - - output logic[31:0] avl_address, - output logic avl_read, - avl_write, - input logic[31:0] avl_readdata, - output logic[31:0] avl_writedata, - input logic avl_waitrequest, - output logic[3:0] avl_byteenable, - input logic avl_irq -); - - enum int unsigned - { - IDLE, - WAIT - } state; - - assign irq = avl_irq; - assign cpu_clk = clk; - assign cpu_rst_n = rst_n; - - assign data_rd = avl_readdata; - - always_comb - unique case(state) - IDLE: ready = 0; - WAIT: ready = !avl_waitrequest; - endcase - - always_ff @(posedge clk or negedge rst_n) - /* P. 16: - * A host must make no assumption about the assertion state of - * waitrequest when the host is idle: waitrequest may be high or - * low, depending on system properties. When waitrequest is asserted, - * host control signals to the agent must remain constant except for - * beginbursttransfer. - */ - if(!rst_n) begin - state <= IDLE; - avl_read <= 0; - avl_write <= 0; - avl_address <= 0; - avl_writedata <= 0; - avl_byteenable <= 0; - end else if((state == IDLE || !avl_waitrequest) && start) begin - state <= WAIT; - avl_read <= ~write; - avl_write <= write; - avl_address <= {addr, 2'b00}; - avl_writedata <= data_wr; - avl_byteenable <= write ? data_be : 4'b1111; - end else if(state == WAIT && !avl_waitrequest) begin - state <= IDLE; - avl_read <= 0; - avl_write <= 0; - end - -endmodule diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv deleted file mode 100644 index 8352435..0000000 --- a/rtl/core/control/mul.sv +++ /dev/null @@ -1,67 +0,0 @@ -`include "core/uarch.sv" - -module core_control_mul -( - input logic clk, - rst_n, - - input insn_decode dec, - input logic mul_ready, - input word rd_value_a, - rd_value_b, - - input ctrl_cycle cycle, - next_cycle, - input logic issue, - - output word mul_a, - mul_b, - mul_c_hi, - mul_c_lo, - output reg_num mul_r_add_hi, - mul_r_add_lo, - output logic mul, - mul_add, - mul_long, - mul_start, - mul_signed -); - - word hold_a, hold_b; - - assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b}; - assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b}; - - always_ff @(posedge clk or negedge rst_n) - if(!rst_n) begin - mul <= 0; - mul_add <= 0; - mul_long <= 0; - mul_start <= 0; - mul_signed <= 0; - mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}}; - mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}}; - - hold_a <= 0; - hold_b <= 0; - end else begin - mul_start <= 0; - - if(next_cycle.issue) begin - mul <= issue && dec.ctrl.mul; - mul_add <= dec.mul.add; - mul_long <= dec.mul.long_mul; - mul_signed <= dec.mul.signed_mul; - mul_r_add_hi <= dec.mul.r_add_hi; - mul_r_add_lo <= dec.mul.r_add_lo; - end else if(next_cycle.mul) - mul_start <= !cycle.mul; - else if(next_cycle.mul_acc_ld) begin - hold_a <= rd_value_a; - hold_b <= rd_value_b; - end - end - - //TODO: mul update_flags - -endmodule diff --git a/rtl/core/control/mul_fu.sv b/rtl/core/control/mul_fu.sv new file mode 100644 index 0000000..8352435 --- /dev/null +++ b/rtl/core/control/mul_fu.sv @@ -0,0 +1,67 @@ +`include "core/uarch.sv" + +module core_control_mul +( + input logic clk, + rst_n, + + input insn_decode dec, + input logic mul_ready, + input word rd_value_a, + rd_value_b, + + input ctrl_cycle cycle, + next_cycle, + input logic issue, + + output word mul_a, + mul_b, + mul_c_hi, + mul_c_lo, + output reg_num mul_r_add_hi, + mul_r_add_lo, + output logic mul, + mul_add, + mul_long, + mul_start, + mul_signed +); + + word hold_a, hold_b; + + assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b}; + assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b}; + + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) begin + mul <= 0; + mul_add <= 0; + mul_long <= 0; + mul_start <= 0; + mul_signed <= 0; + mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}}; + mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}}; + + hold_a <= 0; + hold_b <= 0; + end else begin + mul_start <= 0; + + if(next_cycle.issue) begin + mul <= issue && dec.ctrl.mul; + mul_add <= dec.mul.add; + mul_long <= dec.mul.long_mul; + mul_signed <= dec.mul.signed_mul; + mul_r_add_hi <= dec.mul.r_add_hi; + mul_r_add_lo <= dec.mul.r_add_lo; + end else if(next_cycle.mul) + mul_start <= !cycle.mul; + else if(next_cycle.mul_acc_ld) begin + hold_a <= rd_value_a; + hold_b <= rd_value_b; + end + end + + //TODO: mul update_flags + +endmodule diff --git a/rtl/core/control/psr.sv b/rtl/core/control/psr.sv deleted file mode 100644 index 6616bc9..0000000 --- a/rtl/core/control/psr.sv +++ /dev/null @@ -1,81 +0,0 @@ -`include "core/uarch.sv" - -module core_control_psr -( - input logic clk, - rst_n, - - input insn_decode dec, - input word cpsr_rd, - spsr_rd, - alu_b, - input psr_mode exception_mode, - - input ctrl_cycle cycle, - next_cycle, - input logic issue, - - output logic psr, - psr_saved, - psr_write, - psr_wr_flags, - psr_wr_control, - final_psr_write, - final_restore_spsr, - output word psr_wb, - psr_wr -); - - word exception_spsr; - - assign psr_wb = psr_saved ? spsr_rd : cpsr_rd; - - always_comb begin - psr_write = 0; - - if(next_cycle.issue) - psr_write = final_psr_write || final_restore_spsr; - - if(cycle.escalate || cycle.exception) - psr_write = 1; - - if(cycle.escalate) - //TODO: F (FIQ) no cambia siempre - psr_wr = {24'b0, 3'b110, exception_mode}; - else if(cycle.exception) - psr_wr = exception_spsr; - else - psr_wr = final_restore_spsr ? spsr_rd : alu_b; - end - - always_ff @(posedge clk or negedge rst_n) - if(!rst_n) begin - psr <= 0; - psr_saved <= 0; - psr_wr_flags <= 0; - psr_wr_control <= 0; - - exception_spsr <= 0; - final_psr_write <= 0; - final_restore_spsr <= 0; - end else if(next_cycle.issue) begin - psr <= issue && dec.ctrl.psr; - psr_saved <= dec.psr.saved; - psr_wr_flags <= dec.psr.wr_flags; - psr_wr_control <= dec.psr.wr_control; - - final_psr_write <= issue && dec.psr.write; - final_restore_spsr <= issue && dec.psr.restore_spsr; - end else if(next_cycle.escalate) begin - psr_saved <= 0; - psr_wr_flags <= 0; - psr_wr_control <= 1; - exception_spsr <= cpsr_rd; - end else if(next_cycle.exception) begin - psr <= 0; - psr_saved <= 1; - psr_wr_flags <= 1; - end else if(next_cycle.psr) - psr <= 0; - -endmodule diff --git a/rtl/core/control/status.sv b/rtl/core/control/status.sv new file mode 100644 index 0000000..6616bc9 --- /dev/null +++ b/rtl/core/control/status.sv @@ -0,0 +1,81 @@ +`include "core/uarch.sv" + +module core_control_psr +( + input logic clk, + rst_n, + + input insn_decode dec, + input word cpsr_rd, + spsr_rd, + alu_b, + input psr_mode exception_mode, + + input ctrl_cycle cycle, + next_cycle, + input logic issue, + + output logic psr, + psr_saved, + psr_write, + psr_wr_flags, + psr_wr_control, + final_psr_write, + final_restore_spsr, + output word psr_wb, + psr_wr +); + + word exception_spsr; + + assign psr_wb = psr_saved ? spsr_rd : cpsr_rd; + + always_comb begin + psr_write = 0; + + if(next_cycle.issue) + psr_write = final_psr_write || final_restore_spsr; + + if(cycle.escalate || cycle.exception) + psr_write = 1; + + if(cycle.escalate) + //TODO: F (FIQ) no cambia siempre + psr_wr = {24'b0, 3'b110, exception_mode}; + else if(cycle.exception) + psr_wr = exception_spsr; + else + psr_wr = final_restore_spsr ? spsr_rd : alu_b; + end + + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) begin + psr <= 0; + psr_saved <= 0; + psr_wr_flags <= 0; + psr_wr_control <= 0; + + exception_spsr <= 0; + final_psr_write <= 0; + final_restore_spsr <= 0; + end else if(next_cycle.issue) begin + psr <= issue && dec.ctrl.psr; + psr_saved <= dec.psr.saved; + psr_wr_flags <= dec.psr.wr_flags; + psr_wr_control <= dec.psr.wr_control; + + final_psr_write <= issue && dec.psr.write; + final_restore_spsr <= issue && dec.psr.restore_spsr; + end else if(next_cycle.escalate) begin + psr_saved <= 0; + psr_wr_flags <= 0; + psr_wr_control <= 1; + exception_spsr <= cpsr_rd; + end else if(next_cycle.exception) begin + psr <= 0; + psr_saved <= 1; + psr_wr_flags <= 1; + end else if(next_cycle.psr) + psr <= 0; + +endmodule diff --git a/rtl/core/core.sv b/rtl/core/core.sv new file mode 100644 index 0000000..8d487fa --- /dev/null +++ b/rtl/core/core.sv @@ -0,0 +1,91 @@ +`include "core/uarch.sv" + +module core +( + input logic clk, + rst_n, + + input wire step, + input wire cpu_halt, + output wire cpu_halted, + output wire breakpoint, + + output word avl_address, + output logic avl_read, + avl_write, + input word avl_readdata, + output word avl_writedata, + input logic avl_waitrequest, + output logic[3:0] avl_byteenable, + + input logic avl_irq +); + + logic ready, write, start; + + logic[3:0] data_be; + logic[29:0] addr; + logic[31:0] data_rd, data_wr; + + enum int unsigned + { + IDLE, + WAIT + } state; + + arm810 cpu + ( + .irq(avl_irq), + .halt(cpu_halt), + .halted(cpu_halted), + .bus_addr(addr), + .bus_data_rd(data_rd), + .bus_data_wr(data_wr), + .bus_data_be(data_be), + .bus_ready(ready), + .bus_write(write), + .bus_start(start), +`ifndef VERILATOR + .step(0), + .breakpoint(), +`endif + .* + ); + + assign data_rd = avl_readdata; + + always_comb + unique case(state) + IDLE: ready = 0; + WAIT: ready = !avl_waitrequest; + endcase + + always_ff @(posedge clk or negedge rst_n) + /* P. 16: + * A host must make no assumption about the assertion state of + * waitrequest when the host is idle: waitrequest may be high or + * low, depending on system properties. When waitrequest is asserted, + * host control signals to the agent must remain constant except for + * beginbursttransfer. + */ + if(!rst_n) begin + state <= IDLE; + avl_read <= 0; + avl_write <= 0; + avl_address <= 0; + avl_writedata <= 0; + avl_byteenable <= 0; + end else if((state == IDLE || !avl_waitrequest) && start) begin + state <= WAIT; + avl_read <= ~write; + avl_write <= write; + avl_address <= {addr, 2'b00}; + avl_writedata <= data_wr; + avl_byteenable <= write ? data_be : 4'b1111; + end else if(state == WAIT && !avl_waitrequest) begin + state <= IDLE; + avl_read <= 0; + avl_write <= 0; + end + +endmodule diff --git a/rtl/core/decode/branch.sv b/rtl/core/decode/branch.sv deleted file mode 100644 index 1dbc1ad..0000000 --- a/rtl/core/decode/branch.sv +++ /dev/null @@ -1,18 +0,0 @@ -`include "core/decode/isa.sv" -`include "core/uarch.sv" - -module core_decode_branch -( - input word insn, - - output logic link, - output ptr offset -); - - logic[23:0] immediate; - assign immediate = insn `FIELD_B_OFFSET; - - assign link = insn `FIELD_B_L; - assign offset = {{6{immediate[23]}}, immediate}; - -endmodule diff --git a/rtl/core/decode/branch_dec.sv b/rtl/core/decode/branch_dec.sv new file mode 100644 index 0000000..1dbc1ad --- /dev/null +++ b/rtl/core/decode/branch_dec.sv @@ -0,0 +1,18 @@ +`include "core/decode/isa.sv" +`include "core/uarch.sv" + +module core_decode_branch +( + input word insn, + + output logic link, + output ptr offset +); + + logic[23:0] immediate; + assign immediate = insn `FIELD_B_OFFSET; + + assign link = insn `FIELD_B_L; + assign offset = {{6{immediate[23]}}, immediate}; + +endmodule diff --git a/rtl/core/decode/coproc.sv b/rtl/core/decode/coproc.sv deleted file mode 100644 index 153cadf..0000000 --- a/rtl/core/decode/coproc.sv +++ /dev/null @@ -1,24 +0,0 @@ -`include "core/decode/isa.sv" -`include "core/uarch.sv" - -module core_decode_coproc -( - input word insn, - - output coproc_decode decode, - output reg_num rd, - output logic writeback, - update_flags -); - - assign rd = insn `FIELD_CP_RD; - assign writeback = decode.load && rd != `R15; - assign update_flags = decode.load && rd == `R15; - - assign decode.crn = insn `FIELD_CP_CRN; - assign decode.crm = insn `FIELD_CP_CRM; - assign decode.op1 = insn `FIELD_CP_OPCODE; - assign decode.op2 = insn `FIELD_CP_OPCODE2; - assign decode.load = insn `FIELD_CP_LOAD; - -endmodule diff --git a/rtl/core/decode/coproc_dec.sv b/rtl/core/decode/coproc_dec.sv new file mode 100644 index 0000000..153cadf --- /dev/null +++ b/rtl/core/decode/coproc_dec.sv @@ -0,0 +1,24 @@ +`include "core/decode/isa.sv" +`include "core/uarch.sv" + +module core_decode_coproc +( + input word insn, + + output coproc_decode decode, + output reg_num rd, + output logic writeback, + update_flags +); + + assign rd = insn `FIELD_CP_RD; + assign writeback = decode.load && rd != `R15; + assign update_flags = decode.load && rd == `R15; + + assign decode.crn = insn `FIELD_CP_CRN; + assign decode.crm = insn `FIELD_CP_CRM; + assign decode.op1 = insn `FIELD_CP_OPCODE; + assign decode.op2 = insn `FIELD_CP_OPCODE2; + assign decode.load = insn `FIELD_CP_LOAD; + +endmodule diff --git a/rtl/core/decode/data.sv b/rtl/core/decode/data.sv deleted file mode 100644 index f744972..0000000 --- a/rtl/core/decode/data.sv +++ /dev/null @@ -1,65 +0,0 @@ -`include "core/decode/isa.sv" -`include "core/uarch.sv" - -module core_decode_data -( - input word insn, - - output data_decode decode, - output logic snd_is_imm, - snd_shift_by_reg_if_reg, - writeback, - conditional, - update_flags, - restore_spsr -); - - alu_op op; - reg_num rn, rd; - logic uses_rn; - - assign decode.op = op; - assign decode.rn = rn; - assign decode.rd = rd; - assign decode.uses_rn = uses_rn; - - assign rn = insn `FIELD_DATA_RN; - assign rd = insn `FIELD_DATA_RD; - assign op = insn `FIELD_DATA_OPCODE; - - assign snd_is_imm = insn `FIELD_DATA_IMM; - assign snd_shift_by_reg_if_reg = insn `FIELD_DATA_REGSHIFT; - - always_comb begin - unique case(op) - `ALU_ADC, `ALU_SBC, `ALU_RSC: - conditional = 1; - - default: - conditional = 0; - endcase - - unique case(op) - `ALU_CMP, `ALU_CMN, `ALU_TST, `ALU_TEQ: - writeback = 0; - - default: - writeback = 1; - endcase - - unique case(op) - `ALU_MOV, `ALU_MVN: - uses_rn = 0; - - default: - uses_rn = 1; - endcase - - update_flags = insn `FIELD_DATA_S; - restore_spsr = (rd == `R15) & update_flags; - - if(restore_spsr) - update_flags = 0; - end - -endmodule diff --git a/rtl/core/decode/data_dec.sv b/rtl/core/decode/data_dec.sv new file mode 100644 index 0000000..f744972 --- /dev/null +++ b/rtl/core/decode/data_dec.sv @@ -0,0 +1,65 @@ +`include "core/decode/isa.sv" +`include "core/uarch.sv" + +module core_decode_data +( + input word insn, + + output data_decode decode, + output logic snd_is_imm, + snd_shift_by_reg_if_reg, + writeback, + conditional, + update_flags, + restore_spsr +); + + alu_op op; + reg_num rn, rd; + logic uses_rn; + + assign decode.op = op; + assign decode.rn = rn; + assign decode.rd = rd; + assign decode.uses_rn = uses_rn; + + assign rn = insn `FIELD_DATA_RN; + assign rd = insn `FIELD_DATA_RD; + assign op = insn `FIELD_DATA_OPCODE; + + assign snd_is_imm = insn `FIELD_DATA_IMM; + assign snd_shift_by_reg_if_reg = insn `FIELD_DATA_REGSHIFT; + + always_comb begin + unique case(op) + `ALU_ADC, `ALU_SBC, `ALU_RSC: + conditional = 1; + + default: + conditional = 0; + endcase + + unique case(op) + `ALU_CMP, `ALU_CMN, `ALU_TST, `ALU_TEQ: + writeback = 0; + + default: + writeback = 1; + endcase + + unique case(op) + `ALU_MOV, `ALU_MVN: + uses_rn = 0; + + default: + uses_rn = 1; + endcase + + update_flags = insn `FIELD_DATA_S; + restore_spsr = (rd == `R15) & update_flags; + + if(restore_spsr) + update_flags = 0; + end + +endmodule diff --git a/rtl/core/decode/mul.sv b/rtl/core/decode/mul.sv deleted file mode 100644 index 114b65b..0000000 --- a/rtl/core/decode/mul.sv +++ /dev/null @@ -1,33 +0,0 @@ -`include "core/decode/isa.sv" -`include "core/uarch.sv" - -module core_decode_mul -( - input word insn, - - output mul_decode decode, - output reg_num rd, - rs, - rm, - output logic update_flags -); - - logic long_mul; - reg_num short_rd, rn; - - assign rd = long_mul ? rn : short_rd; - assign rs = insn `FIELD_MUL_RS; - assign rm = insn `FIELD_MUL_RM; - assign update_flags = insn `FIELD_MUL_S; - - assign decode.add = insn `FIELD_MUL_ACC; - assign decode.long_mul = long_mul; - assign decode.signed_mul = insn `FIELD_MUL_SIGNED; - assign decode.r_add_lo = rn; - assign decode.r_add_hi = short_rd; - - assign long_mul = insn `FIELD_MUL_LONG; - assign short_rd = insn `FIELD_MUL_RD; - assign rn = insn `FIELD_MUL_RN; - -endmodule diff --git a/rtl/core/decode/mul_dec.sv b/rtl/core/decode/mul_dec.sv new file mode 100644 index 0000000..114b65b --- /dev/null +++ b/rtl/core/decode/mul_dec.sv @@ -0,0 +1,33 @@ +`include "core/decode/isa.sv" +`include "core/uarch.sv" + +module core_decode_mul +( + input word insn, + + output mul_decode decode, + output reg_num rd, + rs, + rm, + output logic update_flags +); + + logic long_mul; + reg_num short_rd, rn; + + assign rd = long_mul ? rn : short_rd; + assign rs = insn `FIELD_MUL_RS; + assign rm = insn `FIELD_MUL_RM; + assign update_flags = insn `FIELD_MUL_S; + + assign decode.add = insn `FIELD_MUL_ACC; + assign decode.long_mul = long_mul; + assign decode.signed_mul = insn `FIELD_MUL_SIGNED; + assign decode.r_add_lo = rn; + assign decode.r_add_hi = short_rd; + + assign long_mul = insn `FIELD_MUL_LONG; + assign short_rd = insn `FIELD_MUL_RD; + assign rn = insn `FIELD_MUL_RN; + +endmodule diff --git a/rtl/core/regs/map.sv b/rtl/core/regs/map.sv deleted file mode 100644 index 11085d4..0000000 --- a/rtl/core/regs/map.sv +++ /dev/null @@ -1,30 +0,0 @@ -`include "core/uarch.sv" - -module core_reg_map -( - input reg_num r, - input psr_mode mode, - output logic is_pc, - output reg_index index -); - - reg_index usr; - assign usr = {1'b0, r}; - - always_comb begin - index = 5'bxxxxx; - is_pc = r == `R15; - - if(~is_pc) - unique case(mode) - `MODE_USR, `MODE_SYS: index = usr; - `MODE_FIQ: index = r >= 8 ? usr + 7 : usr; - `MODE_IRQ: index = r >= 13 ? usr + 9 : usr; - `MODE_UND: index = r >= 13 ? usr + 11 : usr; - `MODE_ABT: index = r >= 13 ? usr + 13 : usr; - `MODE_SVC: index = r >= 13 ? usr + 15 : usr; - default: ; - endcase - end - -endmodule diff --git a/rtl/core/regs/reg_map.sv b/rtl/core/regs/reg_map.sv new file mode 100644 index 0000000..11085d4 --- /dev/null +++ b/rtl/core/regs/reg_map.sv @@ -0,0 +1,30 @@ +`include "core/uarch.sv" + +module core_reg_map +( + input reg_num r, + input psr_mode mode, + output logic is_pc, + output reg_index index +); + + reg_index usr; + assign usr = {1'b0, r}; + + always_comb begin + index = 5'bxxxxx; + is_pc = r == `R15; + + if(~is_pc) + unique case(mode) + `MODE_USR, `MODE_SYS: index = usr; + `MODE_FIQ: index = r >= 8 ? usr + 7 : usr; + `MODE_IRQ: index = r >= 13 ? usr + 9 : usr; + `MODE_UND: index = r >= 13 ? usr + 11 : usr; + `MODE_ABT: index = r >= 13 ? usr + 13 : usr; + `MODE_SVC: index = r >= 13 ? usr + 15 : usr; + default: ; + endcase + end + +endmodule diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 4d09af8..54c8b95 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -2,6 +2,7 @@ module conspiracion ( input wire clk_clk, input wire rst_n, + input wire halt, `ifdef VERILATOR input wire step, @@ -48,12 +49,7 @@ module conspiracion output wire [7:0] vga_dac_b ); - logic button; - logic[3:0] data_be; - logic[29:0] addr; - logic[31:0] data_rd, data_wr; - logic reset_reset_n, cpu_clk, cpu_rst_n, cpu_halt, - ready, write, start, irq; + logic button, cpu_halt, reset_reset_n; `ifdef VERILATOR assign cpu_halt = halt; @@ -82,38 +78,17 @@ module conspiracion ); `endif - arm810 core - ( - .clk(cpu_clk), - .rst_n(cpu_rst_n), - .halt(cpu_halt), - .halted(cpu_halted), - .bus_addr(addr), - .bus_data_rd(data_rd), - .bus_data_wr(data_wr), - .bus_data_be(data_be), - .bus_ready(ready), - .bus_write(write), - .bus_start(start), -`ifndef VERILATOR - .step(0), - .breakpoint(), -`endif - .* - ); - platform plat ( - .master_0_core_cpu_clk(cpu_clk), - .master_0_core_cpu_rst_n(cpu_rst_n), - .master_0_core_addr(addr), - .master_0_core_data_rd(data_rd), - .master_0_core_data_wr(data_wr), - .master_0_core_data_be(data_be), - .master_0_core_ready(ready), - .master_0_core_write(write), - .master_0_core_start(start), - .master_0_core_irq(irq), +`ifdef VERILATOR + .cpu_0_mp_step(step), + .cpu_0_mp_breakpoint(breakpoint), +`else + .cpu_0_mp_step(0), + .cpu_0_mp_breakpoint(), +`endif + .cpu_0_mp_cpu_halt(cpu_halt), + .cpu_0_mp_cpu_halted(cpu_halted), .pll_0_reset_reset(0), //TODO: reset controller, algún día .pio_0_external_connection_export(pio_leds), .switches_external_connection_export({2'b00, pio_switches}), -- cgit v1.2.3