From ec7649eef16c7f9c3ca4b74a1cea95eb2f524b29 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 27 Sep 2022 15:16:07 -0600
Subject: Fix branching bugs

---
 rtl/core/decode/decode.sv | 10 ++++++----
 rtl/core/regs/file.sv     |  4 ++--
 rtl/core/regs/regs.sv     |  3 ++-
 3 files changed, 10 insertions(+), 7 deletions(-)

(limited to 'rtl')

diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index a202694..af80135 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -18,8 +18,6 @@ module core_decode
 	logic cond_undefined;
 
 	//TODO
-	logic link;
-	ptr offset;
 	core_decode_conds conds
 	(
 		.cond(insn `FIELD_COND),
@@ -27,17 +25,19 @@ module core_decode
 		.*
 	);
 
-	logic branch_link; //TODO
+	logic branch_link;
 
 	core_decode_branch group_branch
 	(
+		.link(branch_link),
+		.offset(branch_offset),
 		.*
 	);
 
 	//TODO
 	logic restore_spsr;
 
-	logic data_writeback, data_update_flags;
+	logic data_writeback, data_update_flags, data_undefined;
 	alu_decode data_alu;
 
 	core_decode_data group_data
@@ -45,6 +45,7 @@ module core_decode
 		.decode(data_alu),
 		.writeback(data_writeback),
 		.update_flags(data_update_flags),
+		.undefined(data_undefined),
 		.*
 	);
 
@@ -70,6 +71,7 @@ module core_decode
 				alu = data_alu;
 				writeback = data_writeback;
 				update_flags = data_update_flags;
+				undefined = undefined | data_undefined;
 			end
 
 			`INSN_MUL: ;
diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
index e2bcc09..b2dd634 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/regs/file.sv
@@ -18,9 +18,9 @@ module core_reg_file
 
 	assign rd_value = overwrite_hold ? wr_value_hold : q;
 
-	always @(posedge clk) begin
+	always @(negedge clk) begin
 		if(wr_enable) begin
-			file[rd_index] <= wr_value;
+			file[wr_index] <= wr_value;
 			wr_value_hold <= wr_value;
 		end
 
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
index 182b240..247c120 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/regs/regs.sv
@@ -30,6 +30,7 @@ module core_regs
 	assign pc_word = {pc_visible, 2'b00};
 	assign rd_value_a = rd_pc_a ? pc_word : file_rd_value_a;
 	assign rd_value_b = rd_pc_b ? pc_word : file_rd_value_b;
+	assign file_wr_enable = wr_enable & ~wr_pc;
 	assign branch = wr_enable & wr_pc;
 
 	core_reg_file a
@@ -44,7 +45,7 @@ module core_regs
 	(
 		.rd_index(rd_index_b),
 		.rd_value(file_rd_value_b),
-		.wr_enable(wr_enable & ~wr_pc),
+		.wr_enable(file_wr_enable),
 		.*
 	);
 
-- 
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