From d7648e97a20229cdbc4c25b3d446f020e9b4a229 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 2 Oct 2022 09:53:00 -0600 Subject: Use @(posedge clk) in register files --- rtl/core/regs/file.sv | 2 +- rtl/top/hps_sdram_test.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'rtl') diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv index 22f7ccf..a296f5e 100644 --- a/rtl/core/regs/file.sv +++ b/rtl/core/regs/file.sv @@ -14,7 +14,7 @@ module core_reg_file // Ver comentario en uarch.sv word file[30]; - always @(negedge clk) begin + always_ff @(posedge clk) begin if(wr_enable) file[wr_index] <= wr_value; diff --git a/rtl/top/hps_sdram_test.sv b/rtl/top/hps_sdram_test.sv index dbab472..28d6175 100644 --- a/rtl/top/hps_sdram_test.sv +++ b/rtl/top/hps_sdram_test.sv @@ -60,7 +60,7 @@ module hps_sdram_test assign data_wr[7:0] = out; assign write = dir; - always @(posedge clk_clk) unique case(state) + always_ff @(posedge clk_clk) unique case(state) IDLE: begin state <= RELEASE; -- cgit v1.2.3