From d1b10aa380578b5af20081dd37f2d36ec111cbd2 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 30 Sep 2023 00:07:20 -0600 Subject: platform: implement SMP controller --- rtl/debounce.sv | 5 +-- rtl/mp/mp_ctrl.sv | 73 ------------------------------------------ rtl/mp/pe.sv | 47 --------------------------- rtl/smp/pe.sv | 47 +++++++++++++++++++++++++++ rtl/smp/smp_ctrl.sv | 84 +++++++++++++++++++++++++++++++++++++++++++++++++ rtl/top/conspiracion.sv | 28 ++--------------- 6 files changed, 136 insertions(+), 148 deletions(-) delete mode 100644 rtl/mp/mp_ctrl.sv delete mode 100644 rtl/mp/pe.sv create mode 100644 rtl/smp/pe.sv create mode 100644 rtl/smp/smp_ctrl.sv (limited to 'rtl') diff --git a/rtl/debounce.sv b/rtl/debounce.sv index 919588a..434d056 100644 --- a/rtl/debounce.sv +++ b/rtl/debounce.sv @@ -2,13 +2,14 @@ module debounce ( input logic clk, dirty, + output logic clean ); logic last; - // 168ms para reloj de 50MHz - logic[22:0] clean_for; + // 671ms para reloj de 50MHz + logic[24:0] clean_for; always @(posedge clk) begin last <= dirty; diff --git a/rtl/mp/mp_ctrl.sv b/rtl/mp/mp_ctrl.sv deleted file mode 100644 index 362e450..0000000 --- a/rtl/mp/mp_ctrl.sv +++ /dev/null @@ -1,73 +0,0 @@ -module mp_ctrl -( - input logic clk, - rst_n, - - input logic avl_read, - avl_write, - input logic[31:0] avl_writedata, - output logic[31:0] avl_readdata, - - input logic cpu_halted_0, - cpu_halted_1, - cpu_halted_2, - cpu_halted_3, - input logic breakpoint_0, - breakpoint_1, - breakpoint_2, - breakpoint_3, - - output logic halt_0, - halt_1, - halt_2, - halt_3, - step_0, - step_1, - step_2, - step_3 -); - - logic write; - logic[7:0] readdata_3, readdata_2, readdata_1, readdata_0, - writedata_3, writedata_2, writedata_1, writedata_0; - - assign avl_readdata = {readdata_3, readdata_2, readdata_1, readdata_0}; - assign {writedata_3, writedata_2, writedata_1, writedata_0} = avl_writedata; - - // No hay addresses - assign write = avl_write; - - mp_pe pe_1 - ( - .step(step_1), - .halt(halt_1), - .cpu_halted(cpu_halted_1), - .breakpoint(breakpoint_1), - .readdata(readdata_1), - .writedata(writedata_1), - .* - ); - - mp_pe pe_2 - ( - .step(step_2), - .halt(halt_2), - .cpu_halted(cpu_halted_2), - .breakpoint(breakpoint_2), - .readdata(readdata_2), - .writedata(writedata_2), - .* - ); - - mp_pe pe_3 - ( - .step(step_3), - .halt(halt_3), - .cpu_halted(cpu_halted_3), - .breakpoint(breakpoint_3), - .readdata(readdata_3), - .writedata(writedata_3), - .* - ); - -endmodule diff --git a/rtl/mp/pe.sv b/rtl/mp/pe.sv deleted file mode 100644 index f50ed2f..0000000 --- a/rtl/mp/pe.sv +++ /dev/null @@ -1,47 +0,0 @@ -module mp_pe -#(parameter IS_BSP=0) -( - input logic clk, - rst_n, - - input logic write, - input logic[7:0] writedata, - output logic[7:0] readdata, - - input logic cpu_halted, - breakpoint, - - output logic halt, - step -); - - struct packed - { - logic step, halt, run; - } req; - - struct packed - { - logic breakpoint, cpu_halted; - } status; - - assign req = writedata[$bits(req) - 1:0]; - assign readdata = {{(8 - $bits(status)){1'b0}}, status}; - - always @(posedge clk or negedge rst_n) - if (!rst_n) begin - halt <= IS_BSP ? 0 : 1; // Boot es single-core - step <= 0; - status <= {($bits(status)){1'b0}}; - end else begin - status.breakpoint <= breakpoint; - status.cpu_halted <= cpu_halted; - - //Se hace halt hasta el siguiente ciclo después de que se - //solicita el breakpoint - step <= !breakpoint || (req.step && write); - halt <= (halt || breakpoint || (req.halt && write)) - && !((req.run || req.step) && write); - end - -endmodule diff --git a/rtl/smp/pe.sv b/rtl/smp/pe.sv new file mode 100644 index 0000000..f50ed2f --- /dev/null +++ b/rtl/smp/pe.sv @@ -0,0 +1,47 @@ +module mp_pe +#(parameter IS_BSP=0) +( + input logic clk, + rst_n, + + input logic write, + input logic[7:0] writedata, + output logic[7:0] readdata, + + input logic cpu_halted, + breakpoint, + + output logic halt, + step +); + + struct packed + { + logic step, halt, run; + } req; + + struct packed + { + logic breakpoint, cpu_halted; + } status; + + assign req = writedata[$bits(req) - 1:0]; + assign readdata = {{(8 - $bits(status)){1'b0}}, status}; + + always @(posedge clk or negedge rst_n) + if (!rst_n) begin + halt <= IS_BSP ? 0 : 1; // Boot es single-core + step <= 0; + status <= {($bits(status)){1'b0}}; + end else begin + status.breakpoint <= breakpoint; + status.cpu_halted <= cpu_halted; + + //Se hace halt hasta el siguiente ciclo después de que se + //solicita el breakpoint + step <= !breakpoint || (req.step && write); + halt <= (halt || breakpoint || (req.halt && write)) + && !((req.run || req.step) && write); + end + +endmodule diff --git a/rtl/smp/smp_ctrl.sv b/rtl/smp/smp_ctrl.sv new file mode 100644 index 0000000..b6123ad --- /dev/null +++ b/rtl/smp/smp_ctrl.sv @@ -0,0 +1,84 @@ +module smp_ctrl +( + input logic clk, + rst_n, + + input logic avl_read, + avl_write, + input logic[31:0] avl_writedata, + output logic[31:0] avl_readdata, + + input logic cpu_halted_0, + cpu_halted_1, + cpu_halted_2, + cpu_halted_3, + input logic breakpoint_0, + breakpoint_1, + breakpoint_2, + breakpoint_3, + + output logic halt_0, + halt_1, + halt_2, + halt_3, + step_0, + step_1, + step_2, + step_3 +); + + logic write; + logic[7:0] readdata_3, readdata_2, readdata_1, readdata_0, + writedata_3, writedata_2, writedata_1, writedata_0; + + assign avl_readdata = {readdata_3, readdata_2, readdata_1, readdata_0}; + assign {writedata_3, writedata_2, writedata_1, writedata_0} = avl_writedata; + + // No hay addresses + assign write = avl_write; + + mp_pe #(.IS_BSP(1)) pe_0 + ( + .step(step_0), + .halt(halt_0), + .cpu_halted(cpu_halted_0), + .breakpoint(breakpoint_0), + .readdata(readdata_0), + .writedata(writedata_0), + .* + ); + + mp_pe pe_1 + ( + .step(step_1), + .halt(halt_1), + .cpu_halted(cpu_halted_1), + .breakpoint(breakpoint_1), + .readdata(readdata_1), + .writedata(writedata_1), + .* + ); + + mp_pe pe_2 + ( + .step(step_2), + .halt(halt_2), + .cpu_halted(cpu_halted_2), + .breakpoint(breakpoint_2), + .readdata(readdata_2), + .writedata(writedata_2), + .* + ); + + mp_pe pe_3 + ( + .step(step_3), + .halt(halt_3), + .cpu_halted(cpu_halted_3), + .breakpoint(breakpoint_3), + .readdata(readdata_3), + .writedata(writedata_3), + .* + ); + +endmodule diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 54c8b95..9467cd7 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -3,13 +3,6 @@ module conspiracion input wire clk_clk, input wire rst_n, - input wire halt, -`ifdef VERILATOR - input wire step, - output wire breakpoint, -`endif - output wire cpu_halted, - output wire [12:0] memory_mem_a, output wire [2:0] memory_mem_ba, output wire memory_mem_ck, @@ -49,10 +42,9 @@ module conspiracion output wire [7:0] vga_dac_b ); - logic button, cpu_halt, reset_reset_n; + logic button, reset_reset_n; `ifdef VERILATOR - assign cpu_halt = halt; assign reset_reset_n = rst_n; assign button = pio_buttons; `else @@ -63,13 +55,6 @@ module conspiracion .clean(reset_reset_n) ); - debounce halt_debounce - ( - .clk(cpu_clk), - .dirty(halt), - .clean(cpu_halt) - ); - debounce button_debounce ( .clk(clk_clk), @@ -80,19 +65,10 @@ module conspiracion platform plat ( -`ifdef VERILATOR - .cpu_0_mp_step(step), - .cpu_0_mp_breakpoint(breakpoint), -`else - .cpu_0_mp_step(0), - .cpu_0_mp_breakpoint(), -`endif - .cpu_0_mp_cpu_halt(cpu_halt), - .cpu_0_mp_cpu_halted(cpu_halted), .pll_0_reset_reset(0), //TODO: reset controller, algún día .pio_0_external_connection_export(pio_leds), .switches_external_connection_export({2'b00, pio_switches}), - //TODO: glitch rst + //FIXME: el glitch de reset .buttons_external_connection_export({7'b0000000, !button}), .sys_sdram_pll_0_sdram_clk_clk(vram_wire_clk), .vga_dac_CLK(vga_dac_clk), -- cgit v1.2.3