From bf746b3ee73081dff0da03a54749d1fd3c0215f6 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 13 Nov 2022 06:53:53 -0600 Subject: Restore clock connections in Platform Designer --- rtl/top/conspiracion.sv | 5 ----- 1 file changed, 5 deletions(-) (limited to 'rtl') diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 090271f..0b68d8c 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -49,9 +49,6 @@ module conspiracion assign cpu_halt = halt; assign reset_reset_n = rst_n; `else - assign pio_leds[0] = reset_reset_n; - assign pio_leds[1] = cpu_halted; - debounce reset_debounce ( .clk(clk_clk), @@ -93,11 +90,9 @@ module conspiracion .master_0_core_write(write), .master_0_core_start(start), .master_0_core_irq(irq), -`ifdef VERILATOR .pll_0_reset_reset(0), //TODO: reset controller, algún día .pll_0_outclk3_clk(vram_wire_clk), .pio_0_external_connection_export(pio_leds), -`endif .* ); -- cgit v1.2.3