From a148430ae145d99ba50a87b6147fa0e6e81cb258 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 23 May 2024 20:23:55 -0600
Subject: rtl/wb2axip: fix endianness in axisgdma

---
 rtl/wb2axip/axisgdma.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'rtl')

diff --git a/rtl/wb2axip/axisgdma.v b/rtl/wb2axip/axisgdma.v
index 09c38b2..4889151 100644
--- a/rtl/wb2axip/axisgdma.v
+++ b/rtl/wb2axip/axisgdma.v
@@ -804,7 +804,8 @@ module	axisgdma #(
 		// {{{
 		.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
 		.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
-		.FETCH_LIMIT(4)
+		.FETCH_LIMIT(4),
+		.SWAP_ENDIANNESS(1'b0) // ???? Por qué estaba en 1 ???
 		// }}}
 	) pf (
 		// {{{
-- 
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