From 887d3872491fd80da9ec1c6963e5c2809fe3522c Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 6 Nov 2022 15:48:50 -0600
Subject: Move multiplication logic out of control.sv

---
 rtl/core/control/control.sv | 13 ++++++-------
 rtl/core/control/mul.sv     | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 7 deletions(-)
 create mode 100644 rtl/core/control/mul.sv

(limited to 'rtl')

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index d214525..49c1e8b 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -105,6 +105,11 @@ module core_control
 		.*
 	);
 
+	core_control_data ctrl_mul
+	(
+		.*
+	);
+
 	logic final_writeback, final_update_flags;
 	reg_num final_rd;
 
@@ -126,14 +131,8 @@ module core_control
 
 		unique0 case(next_cycle)
 			ISSUE:
-				if(issue) begin
-					mul <= dec.mul;
-					mul_add <= dec_mul.add;
-					mul_long <= dec_mul.long_mul;
-					mul_signed <= dec_mul.signed_mul;
-
+				if(issue)
 					coproc <= dec.coproc;
-				end
 		endcase
 	end
 
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
new file mode 100644
index 0000000..8d23514
--- /dev/null
+++ b/rtl/core/control/mul.sv
@@ -0,0 +1,35 @@
+`include "core/uarch.sv"
+
+module core_control_mul
+(
+	input  logic           clk,
+
+	input  datapath_decode dec,
+	input  mul_decode      dec_mul,
+	input  logic           mul_ready,
+
+	input  ctrl_cycle      next_cycle,
+	input  logic           issue,
+
+	output logic           mul,
+	                       mul_add,
+	                       mul_long,
+	                       mul_signed
+);
+
+	always_ff @(posedge clk)
+		if(next_cycle == ISSUE && issue) begin
+			mul <= dec.mul;
+			mul_add <= dec_mul.add;
+			mul_long <= dec_mul.long_mul;
+			mul_signed <= dec_mul.signed_mul;
+		end
+
+	initial begin
+		mul = 0;
+		mul_add = 0;
+		mul_long = 0;
+		mul_signed = 0;
+	end
+
+endmodule
-- 
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