From 7d171c1e3ae6dab855ee264e7926281c3a4d25ca Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 10 Nov 2022 20:16:05 -0600
Subject: Add reset debounce

---
 rtl/debounce.sv         | 25 +++++++++++++++++++++++++
 rtl/top/conspiracion.sv | 15 +++++++++++++--
 2 files changed, 38 insertions(+), 2 deletions(-)
 create mode 100644 rtl/debounce.sv

(limited to 'rtl')

diff --git a/rtl/debounce.sv b/rtl/debounce.sv
new file mode 100644
index 0000000..dff9e9e
--- /dev/null
+++ b/rtl/debounce.sv
@@ -0,0 +1,25 @@
+module debounce
+(
+	input  logic clk,
+	             dirty,
+	output logic clean
+);
+
+	logic last;
+	logic[15:0] clean_for;
+
+	always @(posedge clk) begin
+		last <= dirty;
+		clean_for <= last == dirty ? clean_for + 1 : 0;
+
+		if(&clean_for)
+			clean <= last;
+	end
+
+	initial begin
+		last = 0;
+		clean = 0;
+		clean_for = 0;
+	end
+
+endmodule
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 4409d9b..8b29699 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -1,7 +1,7 @@
 module conspiracion
 (
 	input  wire        clk_clk,
-	input  wire        reset_reset_n,
+	input  wire        rst_n,
 	output wire [12:0] memory_mem_a,
 	output wire [2:0]  memory_mem_ba,
 	output wire        memory_mem_ck,
@@ -41,7 +41,18 @@ module conspiracion
 
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_wr;
-	logic cpu_clk, ready, write, start, irq;
+	logic reset_reset_n, cpu_clk, ready, write, start, irq;
+
+`ifdef VERILATOR
+	assign reset_reset_n = rst_n;
+`else
+	debounce reset_debounce
+	(
+		.clk(clk_clk),
+		.dirty(rst_n),
+		.clean(reset_reset_n)
+	);
+`endif
 
 	arm810 core
 	(
-- 
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