From 503957e2883e754fc8424c420c3d9838bd639ed3 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 18 Sep 2022 17:16:46 -0600 Subject: Fix memory simulation --- rtl/bus/master.sv | 2 ++ 1 file changed, 2 insertions(+) (limited to 'rtl') diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv index 5d8c3a8..d350d80 100644 --- a/rtl/bus/master.sv +++ b/rtl/bus/master.sv @@ -26,6 +26,7 @@ module bus_master } state; assign data_rd = avl_readdata; + assign avl_byteenable = 4'b1111; always_ff @(posedge clk) unique case(state) REQUEST: if(start) begin @@ -33,6 +34,7 @@ module bus_master avl_read <= ~write; avl_write <= write; avl_writedata <= data_rw; + state <= WAIT; end WAIT: if(~avl_waitrequest) begin -- cgit v1.2.3