From 1e064f29139a45061a8082914e9ee75c15e803a4 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 22 Nov 2023 01:24:41 -0600 Subject: rtl/gfx: implement fp->fixed conversion --- rtl/gfx/gfx_defs.sv | 2 +- rtl/gfx/gfx_fp_fix.sv | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 rtl/gfx/gfx_fp_fix.sv (limited to 'rtl') diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv index d95414a..913cb85 100644 --- a/rtl/gfx/gfx_defs.sv +++ b/rtl/gfx/gfx_defs.sv @@ -9,7 +9,7 @@ // Target de 200MHz (reloj es 143MHz) con float16, rounding (muy) aproximado `define FP_ADD_STAGES 10 // ~401 LUTs `define FP_MUL_STAGES 5 // ~144 LUTs ~1 bloque DSP -`define FP_INV_STAGES 3 // ~178 LUTs ~1 bloque DSP +`define FP_FIX_STAGES 5 // ~345 LUTs typedef logic[`FLOAT_BITS - 1:0] fp; typedef fp[1:0] vec2; diff --git a/rtl/gfx/gfx_fp_fix.sv b/rtl/gfx/gfx_fp_fix.sv new file mode 100644 index 0000000..b38e0e3 --- /dev/null +++ b/rtl/gfx/gfx_fp_fix.sv @@ -0,0 +1,34 @@ +`include "gfx/gfx_defs.sv" + +module gfx_fp_fix +( + input logic clk, + + input fp in, + input logic stall, + + output fixed out +); + +`ifndef VERILATOR + ip_fp_fix ip_fix + ( + .a(in), + .q(out), + .en(!stall), + .areset(0), + .* + ); +`else + fp pop; + + assign out = $c("taller::fp_fix(", pop, ")"); + + gfx_pipes #(.WIDTH($bits(in)), .DEPTH(`FP_FIX_STAGES)) pipes + ( + .out(pop), + .* + ); +`endif + +endmodule -- cgit v1.2.3