From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 16 May 2024 01:08:04 -0600
Subject: rtl: fix quartus errors: parser, synthesis, fitter

---
 rtl/wb2axip/wbm2axilite.v | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'rtl/wb2axip/wbm2axilite.v')

diff --git a/rtl/wb2axip/wbm2axilite.v b/rtl/wb2axip/wbm2axilite.v
index 6cda44d..222d5ab 100644
--- a/rtl/wb2axip/wbm2axilite.v
+++ b/rtl/wb2axip/wbm2axilite.v
@@ -33,14 +33,14 @@
 ////////////////////////////////////////////////////////////////////////////////
 //
 //
-`default_nettype	none
+//`default_nettype	none
 // }}}
 module wbm2axilite #(
 		// {{{
 		parameter C_AXI_ADDR_WIDTH	=  28,// AXI Address width
-		localparam C_AXI_DATA_WIDTH	=  32,// Width of the AXI R&W data
-		localparam DW			=  C_AXI_DATA_WIDTH,// Wishbone data width
-		localparam AW			=  C_AXI_ADDR_WIDTH-2// WB addr width (log wordsize)
+		/*local*/parameter C_AXI_DATA_WIDTH	=  32,// Width of the AXI R&W data
+		/*local*/parameter DW			=  C_AXI_DATA_WIDTH,// Wishbone data width
+		/*local*/parameter AW			=  C_AXI_ADDR_WIDTH-2// WB addr width (log wordsize)
 		// }}}
 	) (
 		// {{{
@@ -681,5 +681,5 @@ module wbm2axilite #(
 // }}}
 endmodule
 `ifndef	YOSYS
-`default_nettype wire
+//`default_nettype wire
 `endif
-- 
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