From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Thu, 16 May 2024 01:08:04 -0600 Subject: rtl: fix quartus errors: parser, synthesis, fitter --- rtl/wb2axip/aximrd2wbsp.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'rtl/wb2axip/aximrd2wbsp.v') diff --git a/rtl/wb2axip/aximrd2wbsp.v b/rtl/wb2axip/aximrd2wbsp.v index 07dd7a7..bc7811d 100644 --- a/rtl/wb2axip/aximrd2wbsp.v +++ b/rtl/wb2axip/aximrd2wbsp.v @@ -44,7 +44,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module aximrd2wbsp #( // {{{ @@ -52,8 +52,8 @@ module aximrd2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH/8), - localparam AW = C_AXI_ADDR_WIDTH - AXI_LSBS, + /*local*/parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH/8), + /*local*/parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, parameter LGFIFO = 3, parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b0, parameter [0:0] OPT_SIZESEL = 1 -- cgit v1.2.3