From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Thu, 16 May 2024 01:08:04 -0600 Subject: rtl: fix quartus errors: parser, synthesis, fitter --- rtl/wb2axip/axim2wbsp.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'rtl/wb2axip/axim2wbsp.v') diff --git a/rtl/wb2axip/axim2wbsp.v b/rtl/wb2axip/axim2wbsp.v index fb58458..729f5ac 100644 --- a/rtl/wb2axip/axim2wbsp.v +++ b/rtl/wb2axip/axim2wbsp.v @@ -39,7 +39,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module axim2wbsp #( // {{{ @@ -47,9 +47,9 @@ module axim2wbsp #( // This is an int between 1-16 parameter C_AXI_DATA_WIDTH = 32,// Width of the AXI R&W data parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width - localparam AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, - localparam DW = C_AXI_DATA_WIDTH, - localparam AW = C_AXI_ADDR_WIDTH - AXI_LSBS, + /*local*/parameter AXI_LSBS = $clog2(C_AXI_DATA_WIDTH)-3, + /*local*/parameter DW = C_AXI_DATA_WIDTH, + /*local*/parameter AW = C_AXI_ADDR_WIDTH - AXI_LSBS, parameter LGFIFO = 5, parameter [0:0] OPT_SWAP_ENDIANNESS = 1'b0, parameter [0:0] OPT_READONLY = 1'b0, -- cgit v1.2.3