From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 16 May 2024 01:08:04 -0600
Subject: rtl: fix quartus errors: parser, synthesis, fitter

---
 rtl/wb2axip/axilxbar.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'rtl/wb2axip/axilxbar.v')

diff --git a/rtl/wb2axip/axilxbar.v b/rtl/wb2axip/axilxbar.v
index 95c9172..44294b2 100644
--- a/rtl/wb2axip/axilxbar.v
+++ b/rtl/wb2axip/axilxbar.v
@@ -76,7 +76,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////
 //
-`default_nettype none
+//`default_nettype none
 // }}}
 module	axilxbar #(
 		// {{{
@@ -90,8 +90,8 @@ module	axilxbar #(
 		parameter	NS = 8,
 		//
 		// AW, and DW, are short-hand abbreviations used locally.
-		localparam	AW = C_AXI_ADDR_WIDTH,
-		localparam	DW = C_AXI_DATA_WIDTH,
+		/*local*/parameter	AW = C_AXI_ADDR_WIDTH,
+		/*local*/parameter	DW = C_AXI_DATA_WIDTH,
 		// SLAVE_ADDR is a bit vector containing AW bits for each of the
 		// slaves indicating the base address of the slave.  This
 		// goes with SLAVE_MASK below.
@@ -2420,5 +2420,5 @@ module	axilxbar #(
 // }}}
 endmodule
 `ifndef	YOSYS
-`default_nettype wire
+//`default_nettype wire
 `endif
-- 
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