From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 16 May 2024 01:08:04 -0600
Subject: rtl: fix quartus errors: parser, synthesis, fitter

---
 rtl/wb2axip/axilsingle.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'rtl/wb2axip/axilsingle.v')

diff --git a/rtl/wb2axip/axilsingle.v b/rtl/wb2axip/axilsingle.v
index e92db40..8da2685 100644
--- a/rtl/wb2axip/axilsingle.v
+++ b/rtl/wb2axip/axilsingle.v
@@ -101,7 +101,7 @@
 ////////////////////////////////////////////////////////////////////////////////
 //
 //
-`default_nettype none
+//`default_nettype none
 // `ifdef	VERILATOR
 // `define	FORMAL
 // `endif
@@ -112,7 +112,7 @@ module	axilsingle #(
 		parameter	NS = 16,
 		//
 		parameter integer C_AXI_DATA_WIDTH = 32,
-		localparam integer C_AXI_ADDR_WIDTH = $clog2(NS)+$clog2(C_AXI_DATA_WIDTH)-3,
+		/*local*/parameter integer C_AXI_ADDR_WIDTH = $clog2(NS)+$clog2(C_AXI_DATA_WIDTH)-3,
 		//
 		// LGFLEN specifies the log (based two) of the number of
 		// transactions that may need to be held outstanding internally.
@@ -710,5 +710,5 @@ module	axilsingle #(
 `endif
 endmodule
 // `ifndef	YOSYS
-// `default_nettype wire
+// //`default_nettype wire
 // `endif
-- 
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