From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 16 May 2024 01:08:04 -0600
Subject: rtl: fix quartus errors: parser, synthesis, fitter

---
 rtl/wb2axip/axilrd2wbsp.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'rtl/wb2axip/axilrd2wbsp.v')

diff --git a/rtl/wb2axip/axilrd2wbsp.v b/rtl/wb2axip/axilrd2wbsp.v
index 569b5e8..4ba1218 100644
--- a/rtl/wb2axip/axilrd2wbsp.v
+++ b/rtl/wb2axip/axilrd2wbsp.v
@@ -32,15 +32,15 @@
 ////////////////////////////////////////////////////////////////////////////////
 //
 //
-`default_nettype	none
+//`default_nettype	none
 // }}}
 module	axilrd2wbsp #(
 		// {{{
 		parameter C_AXI_DATA_WIDTH	= 32,
 		parameter C_AXI_ADDR_WIDTH	= 28,
 		parameter AXILLSB		= $clog2(C_AXI_DATA_WIDTH/8),
-		localparam	AW		= C_AXI_ADDR_WIDTH-AXILLSB,
-		localparam	DW		= C_AXI_DATA_WIDTH,
+		/*local*/parameter	AW		= C_AXI_ADDR_WIDTH-AXILLSB,
+		/*local*/parameter	DW		= C_AXI_DATA_WIDTH,
 		parameter LGFIFO                =  3
 		// }}}
 	) (
@@ -597,5 +597,5 @@ module	axilrd2wbsp #(
 // }}}
 endmodule
 `ifndef	YOSYS
-`default_nettype wire
+//`default_nettype wire
 `endif
-- 
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