From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 16 May 2024 01:08:04 -0600
Subject: rtl: fix quartus errors: parser, synthesis, fitter

---
 rtl/wb2axip/axilgpio.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'rtl/wb2axip/axilgpio.v')

diff --git a/rtl/wb2axip/axilgpio.v b/rtl/wb2axip/axilgpio.v
index 0a6e90c..92c669a 100644
--- a/rtl/wb2axip/axilgpio.v
+++ b/rtl/wb2axip/axilgpio.v
@@ -84,7 +84,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////
 //
-`default_nettype none
+//`default_nettype none
 // }}}
 module	axilgpio #(
 		// {{{
@@ -93,7 +93,7 @@ module	axilgpio #(
 		// is fixed at a width of 32-bits by Xilinx def'n, and 2) since
 		// we only ever have 4 configuration words.
 		parameter	C_AXI_ADDR_WIDTH = 5,
-		localparam	C_AXI_DATA_WIDTH = 32,
+		/*local*/parameter	C_AXI_DATA_WIDTH = 32,
 		// OPT_SKIDBUFFER will increase throughput to 100% from 50%
 		parameter [0:0]	OPT_SKIDBUFFER = 1'b1,
 		// OPT_LOWPOWER will force RDATA to zero if ever !RVALID
-- 
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