From d2fc80b6d8b4a64efa00c8458ae94f6b44ddf6be Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 20 Dec 2022 16:16:08 -0600 Subject: Fix clock/reset timing in single-step, dsp_mul --- rtl/top/conspiracion.sv | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'rtl/top') diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index c9e940f..4d09af8 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -3,9 +3,12 @@ module conspiracion input wire clk_clk, input wire rst_n, input wire halt, +`ifdef VERILATOR input wire step, - output wire cpu_halted, output wire breakpoint, +`endif + output wire cpu_halted, + output wire [12:0] memory_mem_a, output wire [2:0] memory_mem_ba, output wire memory_mem_ck, @@ -92,6 +95,10 @@ module conspiracion .bus_ready(ready), .bus_write(write), .bus_start(start), +`ifndef VERILATOR + .step(0), + .breakpoint(), +`endif .* ); -- cgit v1.2.3